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Interrupt Functions
Section 7-2
7-2
Interrupt Functions
7-2-1
Overview
The Customizable Counter Unit supports the following interrupts.
Executing Interrupt Programs in the Customizable Counter Unit
The interrupt routines that are executed for all of the following interrupts are
programmed as subroutines. Subroutines are defined between SBN(92) and
RET(93) following the main program.
Input Interrupts
Contact inputs 0 to 3 to the Customizable Counter Unit can be set as interrupt
inputs. If they are set for Input Interrupt Mode, an interrupt will be generated
when the input turns ON, OFF, or both. If they are set for Counter Mode, an
interrupt will be generated when a specified counter value is reached.
Interval Timer Interrupts
An interrupt will be generated for an interval timer that can be set to a preci-
sion of 0.1 ms.
High-speed Counter
Interrupts
An interrupt will be generated when the PV of the counter equals a preset tar-
get value.
Pulse Output Interrupts
An interrupt will be generated when the PV of the pulse output equals a preset
target value.
Note
Other than interrupts, bit patterns can also be output internally when the PV is
within a specified range in Range Comparison Mode. High-speed counter
PVs, pulse output PVs, pulse counter timer PVs, and one-shot pulse elapsed
times can be used as the PVs for bit pattern output.
Executing Interrupt Programs in the CPU Unit
The MCRO instruction can be executed in the Customizable Counter Unit to
generate an external interrupt to the CPU Unit to execute an external interrupt
task.
7-2-2
Interrupt Priority
The specified subroutine will be executed when an interrupt is generated. The
priority of interrupts is shown below.
If an interrupt with a higher priority occurs when an interrupt is being pro-
cessed, the current interrupt will be interrupted to execute the higher-priority
interrupt. When the subroutine for the higher-priority interrupt has been com-
pleted, processing of the previous interrupt will be continued.
If an interrupt with the same or a lower priority occurs when an interrupt is
being processed, the current interrupt will be completed and then the new
interrupt will be processed.
If interrupts of the same priority occur simultaneously, they will be processed
in the following order.
• Input interrupt 0, Input interrupt 1, Input interrupt 2, Input interrupt 3
• Interval timer interrupt, Pulse output 1 interrupt, Pulse output 2 interrupt,
High-speed counter 1 interrupt, High-speed counter 2 interrupt
An instruction controlling a port operation cannot be programmed in a subrou-
tine if an instruction in the main program is already controlling pulse I/O or a
high-speed counter for the same port. If this is attempted, SR 25503 will turn
ON. The following instructions are included: INI, PRV, CTBL, SPED, PULS,
PLS2, ACC, and STIM.
Input interrupts
Interval timer
interrupts
Pulse output
interrupts
High-speed
counter interrupts
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Summary of Contents for CS1W-HCA12-V1
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Page 6: ...vi...
Page 20: ...xx Conformance to EC Directives 7...
Page 38: ...18 Models and System Configurations Section 1 2...
Page 78: ...58 Fail safe Circuits Section 3 5...
Page 138: ...118 AR Area Section 6 4...
Page 204: ...184 Improved Instructions Section 7 14...
Page 222: ...202 Cycle Time Section 8 3...
Page 240: ...220 Troubleshooting Flowcharts Section 9 5...
Page 244: ...224 Precautions when Using the CX Programmer Appendix A...
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