Omron CP1L-EL20DR-D, Operation Manual

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Data Registers Section 4-12
4-12 Data Registers
The sixteen Data Registers (DR0 to DR15) are used to offset the PLC mem-
ory addresses in Index Registers when addressing words indirectly.
The value in a Data Register can be added to the PLC memory address in an
Index Register to specify the absolute memory address of a bit or word in I/O
memory. Data Registers contain signed binary data, so the content of an
Index Register can be offset to a lower or higher address.
Normal instructions can be used to store data in Data Registers.
Forcing Bit Status Bits in Data Registers cannot be force-set and force-reset.
Examples The following examples show how Data Registers are used to offset the PLC
memory addresses in Index Registers.
LD DR0 ,IR0 Adds the contents of DR0 to the contents
of IR0 and loads the bit at that PLC mem-
ory address.
MOV(021) #0001 DR0 ,IR1 Adds the contents of DR0 to the contents
of IR1 and writes #0001 to that PLC
memory address.
Range of Values The contents of data registers are treated as signed binary data and thus
have a range of –32,768 to 32,767.
Data Register Initialization The Data Registers will be cleared in the following cases:
1. When the operating mode is changed from PROGRAM mode to
RUN/MONITOR mode or vice-versa and the IOM Hold Bit is OFF
2. When the power is cycled and the IOM Hold Bit is OFF or not protected in
the PLC Setup
IOM Hold Bit Operation If the IOM Hold Bit (A500.12) is ON, the Data Registers won’t be cleared
when a FALS error occurs or the operating mode is changed from PROGRAM
mode to RUN/MONITOR mode or vice-versa.
If the IOM Hold BIt (A500.12) is ON and the PLC Setup’s “IOM Hold Bit Status
at Startup” setting is set to protect the IOM Hold Bit, the Data Registers won’t
be cleared when the PLC’s power supply is reset (ON
→
OFF
→
ON).
Set to a base value
with MOVR(560) or
MOVRW(561).
Set with a regular
instruction.
Pointer
I/O Memory
Hexadecimal content Decimal equivalent
8000 to FFFF –32,768 to –1
0000 to 7FFF 0 to 32,767