Omron CJ1W-CTL41-E, Operation Manuals

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Appendix C
Application Restrictions
The following restrictions apply when using CJ1W-CTL41-E Counter Units.
Restriction Reference
The Open Gate Bit, Close Gate Bit, Preset Counter Bit, Reset Bit, or the Counter
Capture Bit in CIO may not be executed if turned ON for only one PLC-cycle. Always
keep these bits turned ON until the execution status changes in the corresponding
flag in n+21, n+25, n+29 and n+33. 3-4 "Controlling a Counter"
4-2 "Memory Allocation"
The comparison operation stops for 1.5 ms from when the Counter Value falls within
the Upper Range Limit or Lower Range Limit for the Range Data. However, the
comparison does not stop for other counters.
This time should be taken in consideration when making settings for Range Data. 3-5-1-2 "Configuration and operation
in Range Mode"
When the Counter Value reaches the target value for Comparison Data, comparison
stops for 1.5 ms. However, comparison for other counters does not stop.
This time should be taken in consideration when making settings for Comparison
Data. 3-5-2-2 "Configuration and operation
in Comparison Mode"
Comparison is stopped during the execution of IOWR/IORD-instructions and remains
stopped until the processing of the instruction has been completed. The Data
Transfer Busy bit is ON during this time.
This stopping of comparison during the execution of IOWR/IORD-instructions affects
counter comparisons for all counters.
Set Range Data and Comparison Data considering that comparisons are stopped by
execution of IOWR/IORD-instructions. 3-5-1-2 "Configuration and operation
in Range Mode"
3-5-2-2 "Configuration and operation
in Comparison Mode"
The I/O Refresh will not occur while the Data Transfer Busy bit (CIO n+17, bit 02) is
ON, and the Counter Value will not be refreshed while this bit is ON. 4-1-1 "Basic Setup"
The Unit's Data Transfer Busy bit (n+17, bit 02) will turn ON for approximately 120 ms
at restart and when the power is turned ON. 4-2-3 "CIO-Memory Mapping"
When using the IOWR-instruction to write Comparison Data to the Unit, check that
the target value being written will not be duplicated in the same Counter. If a target
value already set to the Unit is transferred, set the Comparison Data so that the same
value will be overwritten for the existing target value. 4-5 "Supported IOWR/IORD-
Instructions"
A CJ1G-CPU
@@
H, CJ1H-CPU
@@
H or CJ1M-CPU
@@
CPU Unit is required to use
external interrupt tasks. CJ1G-CPU @@ CPU Units (Without the H suffix) do not
support external interrupt tasks.
There are also restrictions on the position of the Unit on the Rack. Refer to the
section given in the right column for information on the restrictions.
4-6 "Interrupts"
The External Interrupt Task buffer can store up to 30 requests. 5-2-5 "Interrupt FIFO full error"