Omnivision CameraChip OV9650, Implementation Manual

Page: 46 / 56

46 Proprietary to OmniVision Technologies Version 1.1, December 7, 2004
OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChip™ O
mni ision
1D MIDL A2 R Manufacturer ID Byte – Low (Read only = 0xA2)
1E MVFP 00 RW
Mirror/VFlip Enable
Bit[7:6]: Reserved
Bit[5]:
Mirror
0:
Normal image
1: Mirror image
Bit[4]: VFlip enable
0:
VFlip disable
1: VFlip enable
Bit[3:0]: Reserved
1F LAEC 00 RW Reserved
20 BOS 80 RW
B Channel ADBLC Result
Bit[7]: Offset adjustment sign
0:
Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range (high 7 bits)
21 GBOS 80 RW
Gb channel ADBLC result
Bit[7]: Offset adjustment sign
0:
Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range
22 GROS 80 RW
Gr channel ADBLC result
Bit[7]: Offset adjustment sign
0:
Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range
23 ROS 80 RW
R channel ADBLC result
Bit[7]: Offset adjustment sign
0:
Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range
24 AEW 78 RW AGC/AEC - Stable Operating Region (Upper Limit)
25 AEB 68 RW AGC/AEC - Stable Operating Region (Lower Limit)
26 VPT D4 RW
AGC/AEC Fast Mode Operating Region
Bit[7:4]: High nibble of upper limit
Bit[3:0]: High nibble of lower limit
27 BBIAS 80 RW
B Channel Signal Output Bias (effective only when COM6 [0] = 1)
Bit[7]: Bias adjustment sign
0:
Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range
Table 10-2. Device Control Register List (Continued)
Address
(Hex)
Register
Name
Default
(Hex) R/W Description