2.5.1
Internal Clock
Sampling rates for the internal clock can be calculated using the following equation:
t = 100ns * [N1*N2] or
f = 10MHz / [N1*N2]
where N1 is the low 16-bits of the clock divider and N2 is the high 16-bits of the clock
divider. The following criteria must be met when selecting values for N1 and N2:
2 < N1 < 65,535
2 < N2 < 65,535
N1 * N2 > 100
Using the equations above, the minimum and maximum data sampling rates for the internal
clock can be calculated.
Maximum sampling rate:
Minimum Sampling Rate:
N1 = 2, N2 = 50
N1 = 65535, N2 = 65535
t = 100 x 10 * [(2)*(50)]
t = 100 x 10 * [(65535)*(65535)]
−
9
−
9
t = 100 x 10 * 100
t = 100 x 10 * [4.295 x 10 ]
−
9
−
9
9
t = 10 us
t = 429.5 sec
f = 10 x 10 / [(2)*(50)]
f = 10 x 10 / [(65535)*(65535)]
6
6
f = 10 x 10 / 100
f = 10 x 10 / [4.295 x 10 ]
6
6
9
f = 100 Khz
f = 2.328 mHz
If extremely slow data sampling rates are needed, the third 8254 timer, the multi-function
timer, can be cascaded with the other two to produce a 48-bit clock divider. The sampling
rates are then calculated as follows:
t = 100ns * [N1*N2*N3] or
f = 10MHz / [N1*N2*N3]
where N1 is the low 16-bits of the clock divider, N2 is the intermediate 16-bits of the clock
divider, and N3 is the high 16-bits of the divider. The following criteria must be met when
selecting values for N1, N2, and N3:
2 < N1 < 65,535
2 < N2 < 65,535
2 < N3 < 65,535
N1 * N2 * N3 > 100
DAQ-16 Users Manual 18
