The first-in, first-out (FIFO) buffer is between the raster buffer and the serial dot data of the video
interface (WDATA).
The CPU can transfer data from the raster buffer to the FIFO automatically when the CPU reads
the "OR-ING" memory area of the raster buffer. The CPU reads a line of data from the raster
buffer before the LSYNC signal is received from the Engine Controller Board.
Once LSYNC is received, reading starts. Then, in response to WCLK, parallel to serial conversion
and data transfer take place.
The amount of data that is read from the FIFO is sensed by the 64NC22VIA counter. The CPU
writes another line of data to the FIFO, immediately after a line of data is read from the FIFO.
Engine I/F Processing
The engine I/F is divided into the engine control signal and the command interface. The engine
control signal is allocated to a signal line through bits of the TTL register. The CPU can obtain the
engine status by sensing each bit, or run the engine by manipulating each bit.
The command I/F is a bidirectional serial signal. The TTL register is used for serial-parallel or
parallel-serial conversion.
Operation Panel Control
The operation panel I/F is a bidirectional serial signal. Each signal line is allocated to the IOA port.
The CPU then sends the shift clock and executes serial or serial-parallel conversion.
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