Oki Okipage 8p, Maintenance Manual, Page: 135 / 190

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Instruction Start bit Operation Address Data
code
Read (READ) 1 10 A5 to A0
Write Enabled (WEN) 1 00 11XXXX
Write (WRITE) 1 01 A5 to A0 D15 to D0
Write All Address (WRAL) 1 00 01XXXX D15 to D0
Write Disabled (WDS) 1 00 00XXXX
Erase 1 11 A5 to A0
Chip Erasable (ERAL) 1 00 10XXXX
3.4 EEPROM Control
The BR93LC46A on the main control board is an electrical erasable/programmable ROM of 64-
bit x 16-bit configuration. Data input to and output from the ROM are bidirectionally transferred
in units of 16 bits through I/O port (EEPRMDT-P) in serial transmission synchronized with a clock
signal from the CPU.
The EEPROM operates in the following instruction modes.
Write cycle timing (WRITE)
Read cycle timing (READ)
CPU
SSTXD-P
IC4
EEPRMCSO-P
EEPRMCLK-P
3
154
150
151
2
4
1
DI DO
CS
SK
EEPROM
CS
SK
DI
DO
HIGH-Z
1 2 4 9 10 25
Min. 450 ns
1 0 1
A5 A4 A1 A0 D15 D14 D1 D0
STATUS
BUSY READY
Max. 500 ns
Max. 10 ms
HIGH-Z
1 2
1 1 0
4
9 10
A5 A4 A1 A0
25 26
D15 D14 D1 D0 0 D15 D14
CS
SK
DI
DO