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Oki MSM7586-01, Manual

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¡ Semiconductor

MSM7586-01/03

11/42

High Impedance

High Impedance

(a) Write Data Timing Diagram

(b) Read Data Timing Diagram

DENM

W

EXCKM

DINM

A2

DOUTM

A1

A0

B7

B6

B5

B4

B3

B2

B1

B0

R

A2

A1

A0

B7

B6

B5

B4

B3

B2

B1

B0

DENM

EXCKM

DINM

DOUTM

,

,

Figure 5  Modem Unit MCU Interface I/O Timing

The register map is shown below.

Table 2:  Modem Unit Control Register (CRM0 to 5) Map

R/W: Read/Write enable    R: Read-only register

R7, R6, R5, R4

These are the control register data output pins.
These output the data CRM2 - B7, B6, B5, and B4, respectively.

Register

Name

Address

A2

A1

A0

Data Description

R/W

B7

B6

B5

B4

B3

B2

B1

B0

CRM0

0

0

0

R/W

—

TXC

SEL

MOD

OFF

IFSEL1

IFSEL0

—

TEST1

TEST0

CRM1

0

0

1

R/W

Ich

GAIN3

Ich

GAIN2

Ich

GAIN1

Ich

GAIN0

Qch

GAIN3

Qch

GAIN2

Qch

GAIN1

Qch

GAIN0

CRM2

0

1

0

R/W

R7

R6

R5

R4

—

—

—

—

CRM3

0

1

1

R/W

Ich

Offset4

Ich

Offset3

Ich

Offset2

Ich

Offset1

Ich

Offset0

—

—

—

CRM4

1

0

0

R/W

Qch

Offset3

Qch

Offset2

Qch

Offset1

Qch

Offset0

—

—

—

CRM5

1

0

1

R/W

ICT5

ICT4

ICT3

ICT2

LOCAL

INV1

LOCAL

INV0

ICT1

ICT0

Qch

Offset4

Summary of Contents for MSM7586-01

Page 1: ...fset and gain can be adjusted with respect to the differential I and Q analog outputs Completely digitized p 4 shift QPSK demodulator system ADPCM CODEC Unit ADPCM system built in ITU T Recommendation...

Page 2: ...BSTO SGM SGCT IO2 IO1 SW1 SW2 VDAC SAO GSX3 AIN3 GSX4 AIN4 CODEC MCU interface To each block VOXI TOUT2 TOUT1 RESET PDN3 AGC DGC VDAC VDDC IO7 IO6 SW5 IO5 SW4 IO4 IO3 SW3 EXCKC DENC DINC DOUTC VREF DP...

Page 3: ...M AGC SGCR SGCT AIN1 AIN1 GSX1 IO5 IO6 IO7 AIN2 GSX2 IO1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO2 VFRO PWI AOUT AOUT 21 22 23 24 25 NC TXW TXD TXCO TXCI NC BSTO DGM DGC R7 R6 R5 R4 NC BC...

Page 4: ...to TXCL TXCO outputs a 384 kHz clock pulse which is generated by dividing the TXCL input by 10 The transmit data synchronous to the 384 kHz clock pulse shouldbeinputtotheTXD Inthiscasethedevicesdonotu...

Page 5: ...RM0 B6 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Dn 1 Dn D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Dn 1 Dn Ramprise up 2symbols Ramp Fall down 2 symbols Delay of 6 25 symbols Delay of 6 25 s...

Page 6: ...e at the I pin can be adjusted using CRM3 B7 to B3 Q Q Quadrature modulation signal Q component differential analog outputs Their output levels are 500 mVpp when TXD 0 360 mVpp typ with 1 6 Vdc as the...

Page 7: ...tion State 0 0 1 1 Mode A 1 0 0 Mode D 1 1 1 Mode G Standby Mode Entire system is powered down The control register is reset 0 0 0 Mode B Entire system is powered down The control register is not rese...

Page 8: ...close as possible on the circuit board MCK Master clock input The clock frequency is 19 2 MHz IFIN Modulated signal input for the demodulator block SelecttheIFfrequencycanbeselectedfrom1 2MHz 10 7MHz...

Page 9: ...circuits and two AFC data memory registers If SLS is 0 slot 1 is selected if SLS is 1 slot 2 is selected RPR High speed phase clock control signal input for the clock recovery circuit If this pin is a...

Page 10: ...make any phase corrections AFC AFC information is reset RPR Average number of times AFC is low AFC information is maintained AFC RPR AFC information is maintained The clock recovery circuit starts wit...

Page 11: ...egister R7 R6 R5 R4 These are the control register data output pins These output the data CRM2 B7 B6 B5 and B4 respectively Register Name Address A2 A1 A0 Data Description R W B7 B6 B5 B4 B3 B2 B1 B0...

Page 12: ...nal transmit amplifier See Fig 6 for gain adjustment VFRO AOUT AOUT PWI Used for the receive analog output and the output for receive gain adjustment VFROisanoutputofthereceivefilter AOUT andAOUT ared...

Page 13: ...signal Vo Receive gain VO VVFRO 2 R6 R5 ZL 120 nF 350 W AIN2 GSX2 R4 C2 R3 AOUT R6 AOUT AIN1 1 C1 R1 R2 Reference voltage generator SGCT from DECODER Vi Differential analog input signal R5 1 VFRO 1 SA...

Page 14: ...down theoutputchangesto0V TheexternalSGvoltageifnecessaryshouldbeusedviaabuffer VDDC VDAC CODEC unit 3 V power supply VDDC is supplied to the digital system power supply and VDAC is supplied to the an...

Page 15: ...tput This signal is the output signal after ADPCM encoding and is serially output from MSB synchronous with the rising edge of BCLK and XSYNC This pin is an open drain output which remains in a high i...

Page 16: ...ars at analog output pins The L level indicates the absenceofvoicesignal thebackgroundnoisegeneratedinthisdeviceistransferredtotheanalog output pins The background noise amplitude is set by the contro...

Page 17: ...R A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 DENC EXCKC DINC DOUTC Figure 8 CODEC Unit MCU Interface I O Timing The register map is shown below Register Name Address A2 A1 A0 Data Description R W B7 B6 B5 B4 B3...

Page 18: ...nc Pulse Setting Time Receive Sync Pulse Setting Time Synchronous Signal Width PCM ADPCM Set up Time PCM ADPCM Hold Time Symbol VDD Ta VIH VIL tIr tIf RDL CDL CSG FMCK DMCK FTXC1 FTXC2 FIFCK1 FIFCK2 D...

Page 19: ...n VDD 3 0 V 5 5 11 0 mA IDD3 Mode D When VDD 3 0 V 5 5 11 0 mA IDD4 Mode E When VDD 3 0 V 11 5 23 0 mA IDD5 Mode F When VDD 3 0 V 9 5 19 0 mA IDD6 Mode G When VDD 3 0 V 14 0 28 0 mA Power Supply Curre...

Page 20: ...g continuous 60 dB P900 900 kHz detuning continuous 65 dB Modulation Accuracy EVM 1 0 3 0 rms Demodulator Side IF Input Level IFV IFIN input level 0 4 VDD VPP IFIN Input Impedance RIF 20 kW SGM Output...

Page 21: ...DD 2 7 V to 3 6 V Ta 25 C to 70 C tXDM3 4 0 400 ns Reference C load 50 pF Fig 9 Receive Digital I O Setting Time tRDM1 2 C load 50 pF Fig 10 0 200 ns tM1 50 ns tM2 50 ns tM3 50 ns tM4 50 ns Serial Por...

Page 22: ...X4 VOFC2 20 20 mV GSX1 GSX2 AOUT AOUT GSX3 GSX4 1 2 kW RLC3 GSX3 150 W 100 pF CLC3 GSX3 100 pF VOC2 1 3 VPP AOUT AOUT GSX4 RL 1 2 kW VOC3 1 3 VPP GSX3 RL 150 W Analog Switch OFF Resistance RSWof 50 MW...

Page 23: ...Symbol tSDXC tSDRC Condition Min 0 Typ Max 200 100 Unit ns VDD 2 7 V to 3 6 V Ta 25 C to 70 C tXDC1 tRDC1 0 ns Reference tXDC2 tRDC2 Fig 12 0 ns tC1 50 ns tC2 50 ns tC3 50 ns tC4 50 ns Serial Port Di...

Page 24: ...SD T4 28 SD T5 23 Receive Signal to Distortion Ratio 2 SD R1 SD R2 SD R3 SD R4 SD R5 Transmit Gain Tracking GT T1 0 2 0 2 GT T2 Reference GT T3 0 2 0 2 GT T4 0 5 0 5 GT T5 1 2 1 2 Receive Gain Tracki...

Page 25: ...ransmit VOX Detection Level Accuracy Voice Detection Level Voice silence differential 10 dB 6 AC Characteristics VOX Function PSRRT Noise frequency 0 kHz to 50 kHz 30 dB Power Supply Noise Rejection R...

Page 26: ...r Side Digital I O Timing Serial Port Timing for Microcontroller Interface Figure 11 Modem Unit Serial Control Port Interface tXSM tDSM tDHM 1 2 3 N 2 N 1 N N 1 TXCI TXCO 384 kHz TXW TXD 1 tSXM 2 3 N...

Page 27: ...e 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 0 tXDC1 tXDC2 tWSC tSXC tXSC tSDXC MSB LSB tXSC tSXC tXDC1 tXDC2 MSB LSB tXDC3 tXDC3 tSDXC BCLK XSYNC PCMSO BCLK XSYNC IS 0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6...

Page 28: ...sition Time Mode B Mode C 1 ms Mode D 5 ms Mode F 5 ms PDN1 0 PDN2 0 PDN1 0 PDN2 1 Mode E 40 ms PDN1 1 PDN2 0 Mode G PDN1 1 PDN2 1 Standby mode PDN0 0 Communication mode PDN0 1 Note 40 ms 5 ms Mode A...

Page 29: ...PR PR UW CR CR G G G G G G G G AFC RPR RCW RXD AFC RPR RCW 240 bits 625 ms 64 bits 56 bits 1 Control ch synchronous burst SS PR 64 bits AFC RPR RCW G G G G G G G G R R R R SS SS PR PR PR UW CR CR G G...

Page 30: ...XD is input synchronized to the rise of TXCI APLL is ON 1 TXCI input 3 84 MHz TXCO output 384 kHz TXCI divided by 10 Transmission data TXD is input synchronized to the rise of TXCO APLL is OFF B5 Modu...

Page 31: ...B6 B7 Qch GAIN0 0 0 0 0 0 0 0 Ich GAIN3 0 CRM1 Initial Value Ich GAIN2 Ich GAIN1 Ich GAIN0 Qch GAIN3 Qch GAIN2 Qch GAIN1 CRM1 B7 B6 B5 B4 Description CRM1 B3 B2 B1 B0 0 1 1 1 Amplitude value 1 042 re...

Page 32: ...0 1 39 mV 1 9 mV 0 1 1 0 0 36 mV 1 12 mV 0 1 0 1 1 33 mV 1 15 mV 0 1 0 1 0 30 mV 1 18 mV 0 1 0 0 1 27 mV 1 21 mV 0 1 0 0 0 24 mV 1 24 mV 0 0 1 1 1 21 mV 1 27 mV 0 0 1 1 0 18 mV 1 30 mV 0 0 1 0 1 15 m...

Page 33: ...ystem configuration 0 0 Normal mode 1 1 Local inverted mode B1 Waveform shaping mode switching bit of the oscillator circuit unit clock When using a master clock external input increase the X1 pin inp...

Page 34: ...both powered ON 2 CRC1 ADPCM Unit Operation Mode Settings B7 B6 ADPCM unit compression algorithm selection 0 0 32 kbps 0 1 64 kbps G 711 through 1 0 24 kbps 1 1 16 kbps B5 Transmit side ADPCM reset a...

Page 35: ...B 0 1 0 0 1 1 0 dB 0 1 1 1 0 0 2 dB 1 0 0 1 0 1 4 dB 1 0 1 1 1 0 6 dB 1 1 0 1 1 1 8 dB 1 1 1 4 dB 2 dB 0 dB 2 dB 4 dB 6 dB 8 dB B6 B5 B4 Transmit Side Gain B2 B1 B0 Receive Side Gain 0 0 0 6 dB 0 0 0...

Page 36: ...B2 B1 B0 Tone generator Receive side gain adjustment refer to Table 8 Table 7 Side Tone Gain Settings MSM7586 01 B0 TONE GAIN0 0 B1 TONE GAIN1 B2 TONE GAIN2 B3 TONE GAIN3 B4 TONE ON OFF B5 Side Tone...

Page 37: ...0 0 0 20 dB 0 0 0 34 dB 0 0 1 32 dB 0 0 1 30 dB 0 1 0 28 dB 0 1 0 26 dB 0 1 1 24 dB 1 1 1 22 dB 18 dB 16 dB 14 dB 12 dB 10 dB 8 dB 6 dB B0 0 1 0 1 0 1 0 1 B3 B2 B1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0...

Page 38: ...ne 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1000 Hz Single tone B4 B3 B2 B1 B0 Description 1 0 0 0 0 0 0 0 1 1300 Hz Single tone 0 0 1 0 1333 Hz Single tone 0 0 1 1 0 1 0 0 0 1 0 1...

Page 39: ...to Fig 7 settings 0 160 ms 1 320 ms B3 Receive side VOX input signal 0 Internal background noise transmit 1 Voicereceivesignaltransmit When using this data set the VOXI pin to 0 B2 Receive side backg...

Page 40: ...ndicator MSM7586 01 0 0 Below 60 dBm0 0 1 50 to 60 dBm0 1 0 40 to 50 dBm0 1 1 Above 40 dBm0 MSM7586 03 0 0 Below 50 dBm0 0 1 40 to 50 dBm0 1 0 30 to 40 dBm0 1 1 Above 30 dBm0 Note These outputs are en...

Page 41: ...M VDDC VDAC SGM SGCR SGCT AGC DGC AGM DGM IFIN Q Q I I AIN1 AIN1 GSX1 AIN2 GSX2 AOUT AOUT PWI VFRO SAO AIN3 GSX3 AIN4 GSX4 TOUT1 TOUT2 TOUT3 MCK IFCK X1 100 1 30 29 7 10 11 9 67 8 68 97 2 3 4 5 12 13...

Page 42: ...nting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mountin...

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