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Oki MSM66201, Specification Sheet, Page: 12 / 31

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Oki MSM66201 Specification Sheet Download Page 12

12/30

¡ Semiconductor

MSM66201/66P201/66207/66P207

SFR (Continued)

Note: A 

I

 mark in the address column indicates that there is a bit that does not exist in the

register.

Address

(HEX)

Name

Abbreviated

Name

R/W

8/16-bit

operation

Reset

0062

I

0063

A/D conversion result register 1

ADCR1

0064

I

0065

ADCR2

0066

I

0067

ADCR3

0068

I

0069

ADCR4

006A

I

006B

ADCR5

R

8/16

undefined

006C

I

006D

ADCR6

006E

I

006F

ADCR7

0070

0071

PWMC0

00H

00H

0072

0073

PWM 0 register

PWMR0

00H

00H

0074

0075

PWM 1 counter

PWMC1

00H

00H

0076

0077

PWM 1 register

PWMR1

00H

00H

0078

007A

PWM 0 control register

PWCON0

00H

00H

8

PWM 1 countrol register

PWCON1

R/W

A/D conversion result register 2

A/D conversion result register 4

A/D conversion result register 5

A/D conversion result register 6

A/D conversion result register 7

PWM 0 counter

A/D conversion result register 3

Summary of Contents for MSM66201

Page 1: ...tructions 8 16 bit arithmetic instructions Multiplication and division operation instructions Bit manipulation instructions Bit logic instrucitons ROM table reference instructions Abundant addressing...

Page 2: ...MSM66207 SS MSM66P207 SS 64 pin plastic QFP QFP64 P 1414 0 80 BK MSM66201 GSBK MSM66207 GS BK 68 pin plastic QFJ PLCC QFJ68 P S950 1 27 MSM66201 JS MSM66P201 JS MSM66207 JS MSM66P207 JS 64 pin cerami...

Page 3: ...RESOUT NMI AGND TIMER 0 3 SERIAL PORT TRANSI TION D A D CONV PWM 0 1 INTERRUPT CONT PERIPHERAL CONT WDT SSP LRB PSW ALU ALU CONT ACCUMULATOR TEMPORARY CONSTANTS R MEMORY CONT PC RAP INSTRUCTION DECODE...

Page 4: ...M3IO VDD VREF AGND P5 7 AI7 P5 6 AI6 P5 5 AI5 P5 4 AI4 P5 3 AI3 P5 2 AI2 P5 1 AI1 P5 0 AI0 P4 7 TRNS3 P4 6 TRNS2 P4 5 TRNS1 P4 4 TRNS0 P4 3 PWM1 P4 2 PWM0 P4 1 TM1CK P4 0 TM0CK 45 64 63 62 61 60 59 58...

Page 5: ...PWM1 P4 2 PWM0 P4 1 TM1CK P4 0 TM0CK 64 63 62 61 60 59 58 57 56 55 54 P0 7 AD7 P0 6 AD6 P0 5 AD5 P0 4 AD4 P0 3 AD3 P0 2 AD2 P0 1 AD1 P0 0 AD0 V DD V REF AGND 17 18 19 20 21 22 23 24 25 26 27 WR READY...

Page 6: ...A9 P1 1 A10 P1 2 A11 P1 3 A12 P1 4 A13 P1 5 A14 P1 6 A15 P1 7 P2 0 P2 1 P2 2 CLKOUT P2 3 RESOUT ALE PSEN RD P5 2 AI2 P5 1 AI1 P5 0 AI0 P4 7 TRNS3 P4 6 TRNS2 P4 5 TRNS1 P4 4 TRNS0 P4 3 PWM1 P4 1 TM1CK...

Page 7: ...put output port Each bit can be assigned to input or output I O I O I O TXD Transmitter data output pin I O HLDA HOLD ACKNOWLEDGE the HLDA signal appears in response to the HOLD signal and indicates t...

Page 8: ...level If set to L level the CPU fetches the code from external program memory FLT If FLT is H level ALE WR RD PSEN are set to H level when reset If FLT is set to L ALE WR RD PSEN are set to floating l...

Page 9: ...Bit 13 Half carry flag HC Bit 12 Data descriptor DD Bit 8 Master interrupt priority flag MIP Bit 9 5 4 User flag MIP Bit 2 0 System control base 2 0 SCB2 0 PC LRB SSP 15 0 15 0 X1 X2 DP USP Index Regi...

Page 10: ...020 0021 0022 0023 0024 0025 0026I 0028 0029 002A 002C 002D 002E 002F 0030 0031 Port 0 data register Timer 0 counter P3IO P3SF P4 P4IO TM0 R W 8 undefined Port 0 mode register Port 2 secondary functio...

Page 11: ...A0H SRTM SRTMR SRTMC STCON Serial port transmission baud rate generator register Serial port transmission baud rate generator control register Serial port transmission mode control register Serial por...

Page 12: ...0069 ADCR4 006AI 006B ADCR5 R 8 16 undefined 006CI 006D ADCR6 006EI 006F ADCR7 0070 0071 PWMC0 00H 00H 0072 0073 PWM 0 register PWMR0 00H 00H 0074 0075 PWM 1 counter PWMC1 00H 00H 0076 0077 PWM 1 reg...

Page 13: ...M fordataspace and ROM for program space 1 RAM Addressing Modes for data space 1 1 Register Direct Addressing ROR DP DP Example 1 2 Displacement Addressing a Zero Page 18H SFR 0000H 0018H L A Example...

Page 14: ...ssing MOV 27FH SSP Example 2 ROM Addressing Modes for program space 2 1 Direct Addressing 200H ROM 0200H LC A Example 2 2 Simple Indirect Addressing a Local Register Indirect ROM ER0 LC ER0 A Example...

Page 15: ...inter SSP Indirect ROM SSP LC SSP A Example d Local Register Base LRB Indirect ROM LRB LC LRB A Example e RAM Indirect RAM A 0C0H J ROM Example 0C0H 2 3 Double Indirect Addressing a Data Pointer DP Do...

Page 16: ...direct Addressing with 16 bit Offset a Pointing Register Indirect 1 Data Pointer DP Indirect ROM 0 to 65535 DP LC A 100H DP Example 2 User Stack Pointer USP Indirect ROM 0 to 65535 USP LC A 100H USP E...

Page 17: ...tes External Memory VCAL Table Area 16 bytes MSM66201 3FFFH Data Memory Space 0000H 047FH FFFFH 0000H 007FH 0080H 00BFH 00C0H 047FH SFR Area Special Function Registors PORT A DC TIMER PWM etc 007FH 00...

Page 18: ...in shrink DIP 64 pin QFP 0 3 to VDD 0 3 0 3 to VDD 0 3 0 3 to VREF 930 565 55 to 150 V mW C Analog Ref Voltage VREF 0 3 to VDD 0 3 Ta 85 C per Package 68 pin QFJ 1120 Ta 25 C RECOMMENDED OPERATING CON...

Page 19: ...3 0 3 0 8 0 8 0 4 V L Input Voltage 5 7 L Input Voltage 8 VOH 4 2 4 2 IO 400mA H Output Voltage 1 4 H Output Voltage 2 VOL 0 4 0 4 IO 3 2mA L Output Voltage 1 4 L Output Voltage 2 IO 200mA IO 1 6mA In...

Page 20: ...20 tfW 20 2tfW 20 tfW 40 tfW 40 tfW 40 ns VDD 5V 10 Ta 40 to 85 C Data Delay Time tDD tfW 20 tfW 40 Memory Data Hold Time tMH 0 tfW 20 Memory Data Setup Time tMS 100 High Address Hold Time tAWH tfW 20...

Page 21: ...07 t W CLK tPAD tPW tAAS tAAH tAAD tAPH ALE AD0 7 A8 15 t W PSEN tIS tIH PC0 7 INST0 7 PC8 15 tAW tRAD tRW tAAS tAAH tAAD tAPH AD0 7 A8 15 RD tMS tMH RAP0 7 DIN0 7 RAP8 15 tWAD tWW tAAS tAAH tAAD tAWH...

Page 22: ...SCKW tSTMXS tSTMXH tSRMXS tSRMXH 50 8tfW 8tfW 40 6tfW 20 2tfW 10 50 ns CL 50pF Output Data Setup Time Output Data Hold Time VDD 5V 10 Ta 40 to 85 C Parameter Symbol Condition Min Max Unit Clock OSC Pu...

Page 23: ...6207 66P207 Q R S T U V N O P Q V E F C D E I J K F G H I K 2 3 4 5 0 1 2 5 t W OSC t W tSCKW tSCKW tSTMXS tSTMXH tSRMXH tSRMXS tSCKW tSCKW tSTSXH tSTSXS tSRSXH tSRSXS SCK SDOUT TXD SDIN RXD SCK SDOUT...

Page 24: ...to 85 C VDD 5V Ta 25 C HALT HOLD operation mode Parameter Symbol Condition Min Unit Resolution Crosstalk n EA ER EC See the recommended circuit VR VDD VAG GND 0V Analog input source impedance 5kW One...

Page 25: ...F 0 1 mF 47 mF 0 1 mF 0 1 mF RI Analog Input RI Analog input source impedance 5kW A D Converter conversion characteristics 1 3FF HEX 000 EZ MIN EZ MAX VREF V EF MAX EF MIN Ideal Conversion center line...

Page 26: ...t and full scale respectively Refer to Conversion Characteristics Diagram 1 A D Converter Conversion Characteristics 2 temperature characteristics Conversion Characteristics Conversion Characteristics...

Page 27: ...at in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and...

Page 28: ...ing and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mounting...

Page 29: ...nting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person for the product name package name pin number package code and desired mountin...

Page 30: ...are surface mount type packages which are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales per...

Page 31: ...This datasheet has been download from www datasheetcatalog com Datasheets for electronics components...

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