TWR-KL28Z Hardware Description
TWR-
KL28Z User’s Guide, Rev. 0, 06/2016
NXP Semiconductors
7
Table 3.
Features of MKL28Z512VLL7
Feature
Description
Mixed-signal
capability
- SAR 16-bit analog-to-digital converter (ADC)
- High-speed comparator (CMP) with internal 6-bit digital-to-analog converter (DAC)
- 12-bit digital-to-analog converter (DAC)
- VREF module 1.2 V output
Performance
- 72 MHz ARM Cortex-M0+ core
- Up to 16 channel DMA for peripheral and memory servicing with reduced CPU loading
and faster system throughput
- Cross bar switch enables concurrent multi-master bus accesses, increasing bus
bandwidth
- Independent flash banks allowing concurrent code execution and firmware updating with
no performance degradation or complex coding routines
- Bit manipulation engine (BME) allows execution of single-instruction atomic bit-modify-
write operations on the peripheral address space
Timing and control
- Three timer/PWM modules
– one with six channel, and two with two channels
- Low-power timer
- Real-time clock
- 4-channel 32-bit periodic interrupt timer provides time base for RTOS task scheduler or
trigger source for ADC conversion, provides lifetime timer capability
Human-machine
interface
Connectivity and
communications
- Touch sensing input
- General-purpose input/output up to 54
- USB full-speed OTG controller with on-chip transceiver and 5 V to 3.3 V regulator,
supporting crystal-less recovery
- USB low-voltage regulator supplies up to 120 mA off chip at 3.3 volts to power external
components from 5-volt input
- Three 32-bit LPSPI modules
- Three LPUART modules
- Three LPI2C modules supporting Ultra-Fast mode
- One I
2
S (SAI) module
- FlexIO module
4.3.1. Clock source
The Kinetis MCUs start up to the default reset clock for core/system clock, which is 8 MHz from SIRC.
Software can enable the main external oscillator (EXTAL/XTAL), or to high frequency internal
reference (FIRC) 48 MHz if desired. The external oscillator/resonator can range from 32.768 KHz up to
a 32 MHz. An 8 MHz crystal is the default external source for the SCG oscillator inputs
(XTAL/EXTAL).
4.3.2. Serial port
The primary serial port interface signals are PTA1 and PTA2. These signals are connected to both the
CMSIS-DAP and to the J1 I/O connector.
