NXP Semiconductors TFA9812 Preliminary Data Sheet Download Page 62

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TFA9812_2

Preliminary data sheet

Rev. 02 — 22 January 2009

62 of 66

NXP Semiconductors

TFA9812

BTL stereo Class-D audio amplifier with I

S input

16. Handling information

It is advisable to abide by the normal precautions appropriate to handling MOS devices.

Summary of Contents for TFA9812

Page 1: ...ious soft and hard impact protection mechanisms to ensure an application that is both user friendly and robust A modulation technique is applied for the TFA9812 which supports common mode choke approa...

Page 2: ...gital volume control in Legacy mode n Digital clip level control n Soft and hard mute n Thermal foldback threshold temperature control n De emphasis n Output power limiting control n Polarity switch n...

Page 3: ...VDDA analog supply voltage 8 12 20 V VDDP power supply voltage 8 12 20 V VDDA 3V3 analog supply voltage 3 3 V 3 0 3 3 3 6 V VDDD 3V3 digital supply voltage 3 3 V 3 0 3 3 3 6 V IP supply current soft m...

Page 4: ...6 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input 5 Ordering information Table 2 Ordering information Type number Package Name Description Version TFA9812HN HVQFN48 plasti...

Page 5: ...BOOT1N OUT1N STAB1 BOOT2P STAB1 CONTROL LOGIC 20 21 DRIVER HIGH 12 13 14 VDDP VSSP2 VDDP OUT2P VSSP2 BOOT2N OUT2N STAB2 STAB2 XTALIN XTALOUT MCLK REFERENCES PROTECTION OVP UVP OCP OTP ODP WP CDELAY D...

Page 6: ...1 For test purposes only connect to VSS 8 VSS1 P PCB ground reference 9 STAB2 O Decoupling of internal 11 V regulator for channel 2 drivers 10 VSSP2 P Negative power supply voltage for channel 1 and c...

Page 7: ...ng reference 31 POWERUP I Power up pin to switch between Sleep and other operational modes 32 AVOL I Analog volume control Legacy mode 33 ENABLE I Enable input to switch between 3 state and other oper...

Page 8: ...the volume control is done by an on board Analog to Digital Converter ADC which measures the analog voltage on pin 32 4 The interpolation filter interpolates from 1 fs to the PWM controller sample ra...

Page 9: ...tatic Discharge ESD 8 2 Functional modes 8 2 1 Control modes The two control modes of the TFA9812 are I2C and legacy In I2C mode the I2C format control is enabled In Legacy mode a pin based subset of...

Page 10: ...ut stages will be forced to enter 3 state mode In Sleep mode the DIAG pin will not flag fault modes 1 Clocking faults do not trigger DIAG output 2 Under these conditions soft mute still has to be enab...

Page 11: ...Table 7 shows the supported crystal frequencies in I2S master mode Table 8 shows the supported MCLK frequencies in MCLK mode I2S slave mode Table 9 shows the supported BCK frequencies in BCK mode I2S...

Page 12: ...shown in Section 9 5 7 Legacy 32 8 192 12 288 18 432 576 fs 44 1 11 2896 16 9344 25 4016 576 fs 48 12 288 18 432 27 648 576 fs Table 9 Valid BCK frequencies in I2S slave mode Control mode fs kHz BCK x...

Page 13: ...n Legacy mode is controlled by AVOL pin Fig 3 Power up power down timing external voltage supplies POWERUP pin I2C available ENABLE pin PWM outputs twake td on td mute_off td soft_mute 010aaa219 soft...

Page 14: ...ple rate setting should be selected again 8 3 2 Power down Figure 3 includes the power down timing while Table 11 shows the pin control for enabling power down Putting the TFA9812 into power down is e...

Page 15: ...terface format MSB first Supported in I2C control mode Supported in Legacy control mode Fig 4 Serial interface input and output formats 16 MSB B2 B3 B4 B5 B6 LEFT LSB JUSTIFIED FORMAT 20 BITS WS BCK D...

Page 16: ...n in Table 13 See Section 8 2 1 for details of how to enable Legacy control mode 8 5 Digital signal processing features 8 5 1 Equalizer 8 5 1 1 Equalizer options The equalizer function can be bypassed...

Page 17: ...the TFA9812 equalizer has a second order Regalia Mitra all pass filter structure The structure is shown in Figure 5 The transfer function of this all pass filter is shown in Equation 2 2 A z is the se...

Page 18: ...configuration and should be chosen according to Equation 6 6 A maximum of 12 dB amplification per equalizer stage can be achieved with respect to the input signal Each band of the equalizer is provid...

Page 19: ...5 4 shows the I2C address locations of the controls for various bands of the equalizer Table 15 Equalizer control word construction Word Section Data word1 15 t1 word1 14 4 11 mantissa bits of k1 wor...

Page 20: ...is common and the volume control setting depends on the supply voltage on the pin AVOL 32 8 bit volume control is available per channel This is dB linear down to 124 dB in steps of 0 5 dB The last ste...

Page 21: ...The analog volume control input signal is first order low pass filtered with a time constant of 10 ms in the digital domain Suddenly switching on or switching off volume by setting the control voltage...

Page 22: ...maximum power output value is determined by the value of the high voltage supply Clipping levels see Section 8 5 5 still apply to the maximum levels of reduced output voltage swings In I2C control mod...

Page 23: ...el is determined by the values on the VDDP pins The power amplifiers can be explicitly put into 3 state mode by using the pin ENABLE as shown in Table 19 The ENABLE pin is functional in Legacy mode an...

Page 24: ...temperature is exceeded the output stages are set to 3 state mode The temperature is then checked at 1 s intervals and the output stages will operate normally again once the temperature has dropped b...

Page 25: ...d by a low DIAG pin and by a high DIAG I2C status bit see Section 9 5 10 8 7 8 Lock protection When the selected clock input source MCLK BCK or crystal stops running the TFA9812 is able to detect this...

Page 26: ...7 13 Overview protections Table 21 shows the overview of the protections Table 21 Overview protections Protections Symbol Conditions DIAG pin I2C flag 1 Output Recovering TF programmable max Tj 125 C...

Page 27: ...ice addresses Table 24 shows the register address options for the TFA9812 as part of the 8 bit byte that contains the device address as well as the bit indicator read write_not R W The TFA9812 support...

Page 28: ...wledgement 10 The microcontroller can either assert the stop condition P or continue with a further pair of data bytes repeating step 6 In the latter case the targeted register address will have been...

Page 29: ...ycle Start TFA9812 address R W First register address TFA9812 address R W MS data byte LS data byte More data More data Stop S 11010A2A1 0 A ADDR A Sr 11010A2A1 1 A MS1 A LS1 A NA P Table 27 Top level...

Page 30: ...izer_A4 word_2 0x1E 0x02A5 R W Section 9 5 5 Equalizer_B4 word_1 0x1F 0x4C40 R W Section 9 5 5 Equalizer_B4 word_2 0x20 0x4A80 R W Section 9 5 5 Equalizer_C4 word_1 0x21 0x5040 R W Section 9 5 5 Equal...

Page 31: ...inversion enabled 5 to 4 ROFF 1 0 Filter roll off sharpness 0 Slow filter roll off 2 to 8 fs stop band 0 7619 fs 1 Slow filter roll off 2 to 8 fs stop band 0 7619 fs 2 Fast filter roll off 2 to 8 fs...

Page 32: ...mbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD RSD RSD RSD DI_FOR2 DI_FOR1 DI_FOR0 WS_POL Default 0 0 0 0 0 1 1 0 Table 33 Bit description of register 02h...

Page 33: ...Equalizer bypassed 0 EQ_BND Equalizer 10 band or 5 band configuration selection 0 10 band equalizer configuration enabled 1 5 band equalizer configuration enabled Table 36 Register addresses xxh 04 06...

Page 34: ...5 1 2 14 to 4 Eyy_k1m 10 0 The 11 mantissa bits of the filter parameter k1 see Section 8 5 1 2 3 to 0 Eyy_k1e 3 0 The four exponent bits of the filter parameter k1 see Section 8 5 1 2 Table 39 Bit de...

Page 35: ...4 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD PLIM1 PLIM0 PW_OFF PW_SF1 PW_SF0 PW_CL1 PW_CL0 Default 0 0 0 0 0 1 0 1 Table 42 Bit desc...

Page 36: ...0 0 1 1 1 0 Table 44 Bit description of register 2Dh digital in clock configuration Bit Symbol Description 4 to 1 FSUB 3 0 Sample frequency fs of digital in signal 0 8 kHz 1 11 025 kHz 2 12 kHz 3 16 k...

Page 37: ...description of register 2Dh digital in clock configuration Bit Symbol Description 9 to 0 TEMP 9 0 Temperature of the TFA9812 which can be calculated in C using Temp TFA9812 1023 TEMP 9 0 2 4552 Table...

Page 38: ...ute demute in progress 1 Audio signal muted as result of a soft mute Table 50 Bit description of register 30h miscellaneous status continued Bit Symbol Description Table 51 Functional control support...

Page 39: ...n 8 5 7 Y D 5 Thermal foldback threshold temperature control Section 8 7 1 Y N Table 51 Functional control support in I2C and Legacy control modes continued D fixed control setting determined by defau...

Page 40: ...8 STAB1 10 11 VSSP2 18 19 VDDP 26 27 VSSP1 12 BOOT2N 15 BOOT1P 22 BOOT2P 25 BOOT1N Table 52 Internal circuitry continued Pin Symbol Equivalent circuitry VDDA 3V3 VDDD 3V3 010aaa462 4 41 VSS1 VSS2 REFA...

Page 41: ...UT1N 29 DIAG 30 CDELAY 31 POWERUP 33 ENABLE 34 GAIN 35 CSEL 36 ADSEL2 PLIM2 37 ADSEL1 PLIM1 43 TEST2 Table 52 Internal circuitry continued Pin Symbol Equivalent circuitry 010aaa468 VDDP 13 14 16 17 20...

Page 42: ...aa474 VSS1 VSS2 REFA REFD Exposed die paddle 39 ESD 010aaa475 VSS1 VSS2 REFA REFD Exposed die paddle ESD 45 46 47 VDDD 3V3 Table 53 Limiting values In accordance with the Absolute Maximum Rating Syste...

Page 43: ...OL 1 VSS 0 5 VSS 4 6 V Vesd electrostatic discharge voltage according to the human body model STAB1 and STAB2 with respect to other pins 1750 1750 V all other pins 2 2 kV according to the charge devic...

Page 44: ...pply voltage 3 3 V 3 0 3 3 3 6 V IP supply current soft mute mode with load filter and snubbers connected 1 38 45 mA sleep mode 1 160 270 A IDDA 3V3 analog supply current 3 3 V operating mode I2S slav...

Page 45: ...LOW level input voltage With respect to VSS2 0 3 VDDD 3V3 V Vhys i input hysteresis voltage With respect to VSS2 0 1 VDDD 3V3 V II input current 50 93 A Regulators Vo output voltage STAB1 VSS1 10 11...

Page 46: ...erature 160 C OverVoltage Protection OVP VP ovp overvoltage protection supply voltage 20 22 3 24 V UnderVoltage Protections UVP VP uvp undervoltage protection supply voltage UVP on VDDA 7 7 5 8 V UVP...

Page 47: ...output power per channel THD 10 RL 6 VDDA VDDP 15 V 15 W Continuous time output power per channel THD 1 RL 8 VDDA VDDP 12 V 6 6 W VDDA VDDP 15 V 10 W Continuous time output power per channel THD 10 R...

Page 48: ...e on state resistance per output MOSFET for low and high side 0 28 0 35 max maximum duty factor 0 96 Table 56 AC characteristics continued Unless specified otherwise VDDA VDDP 12 V VDDA 3V3 VDDD 3V3 3...

Page 49: ...ce RDSon On resistance power switch RS Series resistance output inductor tSU STO set up time for STOP condition 0 6 s tBUF bus free time between a STOP and START condition 1 3 s tSU DAT data set up ti...

Page 50: ...t current is internally limited above a level of 3 A minimum During normal operation the output current should not exceed this threshold level of 3 A otherwise the output signal will be distorted The...

Page 51: ...thout running into current limiting Current limiting clipping will avoid audio holes but it causes a distortion comparable to voltage clipping 14 3 Speaker configuration and impedance For a flat frequ...

Page 52: ...VDDP OUT1P OUT1P BOOT1P OUT2N OUT2N ADSEL2 PLIM2 XTALIN XTALOUT V DDA 3V3 STABA REFA V DDA TEST1 V SS1 STAB2 V SSP2 V SSP2 BOOT2N CSEL 24 dB GAIN ENABLE AVOL POWERUP CDELAY DIAG STAB1 V SSP1 V SSP1 BO...

Page 53: ...DP VDDP OUT1P OUT1P BOOT1P OUT2N OUT2N ADSEL2 PLIM2 XTALIN XTALOUT V DDA 3V3 STABA REFA V DDA TEST1 V SS1 STAB2 V SSP2 V SSP2 BOOT2N CSEL GAIN ENABLE AVOL POWERUP CDELAY DIAG STAB1 V SSP1 V SSP1 BOOT1...

Page 54: ...OOT1P OUT2N OUT2N ADSEL2 PLIM2 XTALIN XTALOUT V DDA 3V3 STABA REFA V DDA TEST1 V SS1 STAB2 V SSP2 V SSP2 BOOT2N CSEL 24 dB GAIN ENABLE AVOL POWERUP CDELAY DIAG STAB1 V SSP1 V SSP1 BOOT1N SCL SFOR SDA...

Page 55: ...UT1P BOOT1P OUT2N OUT2N ADSEL2 PLIM2 XTALIN XTALOUT V DDA 3V3 STABA REFA V DDA TEST1 V SS1 STAB2 V SSP2 V SSP2 BOOT2N CSEL GAIN ENABLE AVOL POWERUP CDELAY DIAG STAB1 V SSP1 V SSP1 BOOT1N SCL SFOR SDA...

Page 56: ...a VP 12 V RL 2 6 b VP 12 V RL 2 8 1 fi 6 kHz 2 fi 1 kHz 3 fi 100 Hz 1 fi 6 kHz 2 fi 1 kHz 3 fi 100 Hz c VP 15 V RL 2 6 d VP 15 V RL 2 8 Fig 17 Total harmonic distortion plus noise as a function of ou...

Page 57: ...stortion plus noise as a function of frequency 010aaa484 1 10 1 10 THD N 10 2 f Hz 10 105 104 102 103 010aaa485 1 10 1 10 THD N 10 2 f Hz 10 105 104 102 103 VP 12 V PO 1 W 1 RL 6 15 H 680 F 2 RL 8 15...

Page 58: ...a function of frequency Fig 22 S N ratio as a function of output power 010aaa488 60 40 80 20 0 SVRR dB 100 fi Hz 10 105 104 102 103 1 2 010aaa489 70 80 60 90 100 S N dB 50 Po W channel 10 2 102 10 10...

Page 59: ...RL 2 6 fi 1 kHz THD 10 1 Power limiter 0 dB 2 Power limiter 1 5 dB 3 Power limiter 3 dB 4 Power limiter 4 5 dB 1 Power limiter 0 dB 2 Power limiter 1 5 dB 3 Power limiter 3 dB 4 Power limiter 4 5 dB...

Page 60: ...6 2 RL 2 8 VP 12 V fi 1 kHz po 2 Po 2 Po Pd 1 RL 2 6 2 RL 2 8 Fig 25 Power dissipation as a function of output power Fig 26 Efficiency as a function of output power 010aaa496 1 2 3 P W 0 Po W channel...

Page 61: ...Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included UNIT A 1 max mm 1 0 05 0 00 0 30 0 18 7 1 6 9 5 75 5 45 7 1 6 9 5 75 5 45 5 5 5 5 0 1 A1 DIMENSIONS mm are the origina...

Page 62: ...Preliminary data sheet Rev 02 22 January 2009 62 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input 16 Handling information It is advisable to abide by the normal preca...

Page 63: ...TL stereo Class D audio amplifier with I2S input 17 Revision history Table 59 Revision history Document ID Release date Data sheet status Change notice Supersedes TFA9812_2 20090122 Preliminary data s...

Page 64: ...lt in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications...

Page 65: ...ge protections 24 8 7 6 Overdissipation protection 25 8 7 7 Window protection 25 8 7 8 Lock protection 25 8 7 9 Underfrequency protection 25 8 7 10 Overfrequency protection 25 8 7 11 Invalid BCK prote...

Page 66: ...nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 22 January 2009 Document identifier TFA9812_2 Please be aware that important notices concerning this...

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