NXP Semiconductors TFA9812, Preliminary Data Sheet

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TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 44 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
13. Characteristics
13.1 DC Characteristics
Table 55. DC characteristics
Unless specified otherwise, V
DDA
= V
DDP
= 12 V, V
SSP1
= V
SSP2
= 0 V, V
DDA(3V3)
= V
DDD(3V3)
= 3.3 V,
V
SS1
= V
SS2
= REFD = REFA = 0 V, T
amb
= 25
°
C, R
L
= 8
Ω
, f
i
= 1 kHz, f
s
= 44.1 kHz, f
sw
= 400 kHz, 24-bit I
2
S input data,
MCLK clock mode, typical application diagram ( Figure 13 ).
Symbol Parameter Condition Min Typ Max Unit
Supply voltage
V
DDA
analog supply
voltage 8 12 20 V
V
DDP
power supply voltage 8 12 20 V
V
DDA(3V3)
analog supply
voltage (3.3 V) 3.0 3.3 3.6 V
V
DDD(3V3)
digital supply voltage
(3.3 V) 3.0 3.3 3.6 V
I
P
supply current soft mute mode, with
load, filter and snubbers
connected
[1]
- 38 45 mA
sleep mode
[1]
- 160 270
µ
A
I
DDA(3V3)
analog supply
current (3.3 V) operating mode
I
2
S slave mode - 2 4 mA
I
2
S master mode - 4 6 mA
sleep mode
V
DDA
= V
DDP
= 12 V - 120 -
µ
A
V
DDA
= V
DDP
= 1 V - 40 70
µ
A
I
DDD(3V3)
digital supply current
(3.3 V) operating mode
I
2
S slave mode - 15 25 mA
I
2
S master mode - 25 40 mA
sleep mode;
DATA = WS = BCK =
MLCK = 0 V - 4 30
µ
A
Amplifier output pins; pins OUT1P, OUT1N, OUT2P and OUT2N
|
V
O(offset)
|
output offset voltage soft mute mode - - 5 mV
Power-up pin
V
IH
HIGH-level input
voltage With respect to V
SS1
2.1 - V
DDD(3V3)
V
V
IL
LOW-level input
voltage With respect to V
SS1
−
0.3 - +0.8 V
I
I
input current - 0.1 20
µ
A
MCLK, BCK, WS, DATA pin
V
IH
HIGH-level input
voltage With respect to V
SS2
0.7
×
V
DDD(3V3)
- - V
V
IL
LOW-level input
voltage With respect to V
SS2
- - 0.3
×
V
DDD(3V3)
V
C
i
input capacitance - - 3 pF