NXP Semiconductors T2080RDB-PC, User Manual, Page: 39 / 47

3.1.4 Software version register (SWVER)
Address: 0h base + 3h offset = 3h
Bit 0 1 2 3 4 5 6 7
Read SW_VER
Write
Reset 0 0 0 0 0 0 0 0
SWVER field descriptions
Field Description
0–7
SW_VER
The version field of the CPLD software.
3.1.5 Reset control register (RSTCON)
Address: 0h base + 10h offset = 10h
Bit 0 1 2 3 4 5 6 7
Read SW_RST C293_RST
Reserved
EC1_RST EC2_RST EDC_RST XGT_RST PEX_RST
Write w1c
w1c
w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0
RSTCON field descriptions
Field Description
0
SW_RST
0: No reset occurs.
1: Writing logic 1 will produce whole board reset# signal; this bit can auto clear.
1
C293_RST
0: No reset occurs.
1: Writing logic 1 will produce C293 Coprocessor reset# signal; this bit can auto clear.
2
-
This field is reserved.
3
EC1_RST
0: No reset occurs.
1: Writing logic 1 will produce RGMII PHY1 (RTL82111E-VB) reset# signal; this bit can auto clear.
4
EC2_RST
0: No reset occurs.
1: Writing logic 1 will produce RGMII PHY2 (RTL82111E-VB) reset# signal; this bit can auto clear.
5
EDC_RST
0: No reset occurs.
1: Writing logic 1 will produce 10GEDC PHY(CS4315) reset# signal; this bit can auto clear.
6
XGT_RST
0: No reset occurs.
1: Writing logic 1 will produce 10GBase-T PHY(AQ1202) reset# signal; this bit can auto clear.
7
PEX_RST
0: No reset occurs
1: Writing logic 1 will produce PCIe x4 slot reset# signal; this bit can auto clear.
Chapter 3 CPLD Specification
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 0, 04/2016
Freescale Semiconductor, Inc. 39