NXP Semiconductors SAFE ASSURE Qorivva MPC5601P, Reference Manual

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Chapter 9 Interrupt Controller (INTC)
MPC5602P Microcontroller Reference Manual, Rev. 4
206 Freescale Semiconductor
The software set/clear interrupt registers support the setting or clearing of software configurable interrupt
request. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by
software. Excepting being set by software, this flag bit behaves the same as a flag bit set within a
peripheral. This flag bit generates an interrupt request within the INTC like a peripheral interrupt request.
Writing a ‘1’ to SET
x will leave SET x unchanged at 0 but sets CLR x . Writing a ‘0’ to SET x has no effect.
CLR x is the flag bit. Writing a ‘1’ to CLR x clears it. Writing a ‘0’ to CLR x has no effect. If a ‘1’ is written
simultaneously to a pair of SET x and CLR x bits, CLR x will be asserted, regardless of whether CLR x was
asserted before the write.
9.5.2.6 INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221)
Address Base + 0x0024 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0
CLR
4
0 0 0 0 0 0 0
CLR
5
W SET4 SET5
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0
CLR
6
0 0 0 0 0 0 0
CLR
7
W SET6 SET7
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-7. INTC Software Set/Clear Interrupt Register 4–7 (INTC_SSCIR[4:7])
Table 9-6. INTC_SSCIR[0:7] field descriptions
Field Description
6, 14, 22, 30
SET[0:7]
Set Flag Bits
Writing a ‘1’ sets the corresponding CLR
x bit. Writing a ‘0’ has no effect. Each SET x always will
be read as a ‘0’.
7, 15, 23, 31
CLR[0:7]
Clear Flag Bits
CLR
x is the flag bit. Writing a ‘1’ to CLR x clears it provided that a ‘1’ is not written simultaneously
to its corresponding SET x bit. Writing a ‘0’ to CLR x has no effect.
0 Interrupt request not pending within INTC
1 Interrupt request pending within INTC
Address Base + 0x0040 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PRI0
0 0 0 0
PRI1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0
PRI2
0 0 0 0
PRI3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-8. INTC Priority Select Register 0–3 (INTC_PSR[0:3])