NXP Semiconductors PXN2020, Reference Manual, Page: 964 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-38 Freescale Semiconductor
commands and data from the TX FIFO. The data returned from the bus slave is either used to drive the
parallel output signals or it is stored in the RX FIFO. The CSI configuration allows serialized data and
configuration or diagnostic data to be transferred to a slave device using only one serial link. The DSPI is
in CSI configuration when the DCONF field in the DSPI_MCR is 0b10.
Figure 30-23 shows an example
of how a DSPI can be used with a deserializing peripheral that supports SPI control for control and
diagnostic frames.
Figure 30-23. Example of System using DSPI in CSI Configuration
In CSI configuration, the DSPI transfers DSI data based on DSI Transfer Initiation Control. (See
Section 30.4.4.5, DSI Transfer Initiation Control. ) When there are SPI commands in the TX FIFO, the SPI
data has priority over the DSI frames. When the TX FIFO is empty, DSI transfer resumes.
Two peripheral chip select signals indicate whether DSI data or SPI data is transmitted. The user must
configure the DSPI so that the two CTAR registers associated with DSI data and SPI data assert different
peripheral chip select signals denoted in the figure as PCS
x and PCS y . The CSI configuration is only
supported in master mode.
Data returned from the external slave while a DSI frame is transferred is placed on the parallel output
signals. Data returned from the external slave while an SPI frame is transferred is moved to the RX FIFO.
The TX FIFO and RX FIFO are fully functional in CSI mode.
30.4.5.1 CSI Serialization
Serialization in the CSI configuration is similar to serialization in DSI configuration. The transfer
attributes for SPI frames are determined by the DSPI_CTAR
n register selected by the CTAS field in the
SPI command halfword. The transfer attributes for the DSI frames are determined by the DSPI_CTAR n
register selected by the DSICTAS field in the DSPI_DSICR. Figure 30-24 shows the CSI serialization
logic.
SPI
DSPI master
DSI
Shift register
TX FIFO
TX
priority
control
SIN x
SOUT x
SCK x
PCS x
PCS y
SPI
External slave deserializer
Shift register
frame
Frame
select
logic
SOUT x
SIN x
SCK x
SS x
SS y
DSI
frame