NXP Semiconductors PXN2020, Reference Manual, Page: 927 / 1376

PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-1
Chapter 30
Deserial – Serial Peripheral Interface (DSPI)
30.1 Introduction
The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for
communication between the PXN20 and external devices. The DSPI supports pin-count reduction through
serialization and deserialization of eMIOS channels and memory-mapped registers. The channels and
register content are transmitted using a SPI-like protocol. There are four identical DSPI blocks: DSPI_A,
DSPI_B, DSPI_C, and DSPI_D.
The DSPIs have three configurations:
• Serial peripheral interface (SPI) configuration where the DSPI operates as a basic SPI or as a
queued SPI through the use of internal FIFOs.
• Deserial serial interface (DSI) configuration where the DSPI serializes the parallel input signals
and deserializes received data by placing it on the parallel output signals.
• Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI
configurations interleaving DSI frames with SPI frames, giving priority to SPI frames.
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers
between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or
through host software.
Figure 30-1 shows a DSPI with external queues in system RAM.
Figure 30-1. DSPI with Queues and DMA
System RAM
DSPI
DMA Controller
TX Queue
RX FIFO
TX FIFO
Shift Register
Data
Data
Addr/Ctrl
RX Queue
Data
Data
Addr/Ctrl