NXP Semiconductors PXN2020, Reference Manual, Page: 805 / 1376

Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 27-33
Figure 27-19. Asynchronous/Control Packet Buffering Example
27.4.6.1.1 Packet Reception
When multi-packet buffering is used for receiving asynchronous or control data packets, buffer processing
should be handled in the following manner:
• At the start of buffer processing, the beginning of the Next Buffer becomes the beginning of the
Current Buffer , as CNBCR n [BSA] is loaded into CCBCR n [BCA]. Additionally, the end of the
Next Buffe r becomes the end of the Current Buffer , as CNBCR n [BEA] is loaded into
CCBCR n [BFA] (See Note 1 in Figure 27-19 ).
• A Buffer Start interrupt is generated (CSCR n [STS[3]] set), which informs software that hardware
has updated CCBCR n , cleared the local channel CSCR n [RDY] bit, and is available to accept the
next buffer. Software may then prepare the Next Buffer by writing CNBCR n [BSA],
CNBCR n [BEA], and CSCR n [RDY]. (See Note 2 in Figure 27-19 ).
Packet 1
(First Packet)
Packet 2
Packet 3
Packet N
(Last Packet)
0
BS
BD
BCA
BFA BEA
BFA BEA
BSA BCA
internal register
Note 3
* RX handling only
Note 5A
* RX handling only
Note 4
Note 1
Note 5B
* TX handling only
Note 6
Note 2
Legend
= 16-bit address pointer
= channel interrupt
(Shows RX/TX handling of Asynchronous/Control Packets using the Current Buffer)
Multi-Packet Buffering Example