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FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
26-108
Freescale Semiconductor
To certain message buffer fields, both the application and the controller have access. To ensure data
consistency, a message buffer locking scheme is implemented that is used to control the access to the data,
control, and status bits of a message buffer. The access regions for receive message buffers are depicted in
. A description of the regions is given in
. If an region is active as indicated in
, the access scheme given for that region applies to the message buffer.
Figure 26-127. Receive Message Buffer Access Regions
The trigger bits MBCCSR
n
[EDT] and MBCCSR
n
[LCKT] and the interrupt enable bit MBCCSR
n
[MBIE]
are not under access control and can be accessed from the application at any time. The status bits
MBCCSR
n
[EDS] and MBCCSR
n
[LCKS] are not under access control and can be accessed from the
controller at any time.
The interrupt flag MBCCSR
n
[MBIF] is not under access control and can be accessed from the application
and the controller at any time. controller set access has higher priority.
The controller restricts its access to the regions depending on the current state of the message buffer. The
application must adhere to these restrictions in order to ensure data consistency. The receive message
buffer states are given in
. A description of the message buffer states is given in
,
which also provides the access scheme for the access regions.
The status bits MBCCSR
n
[EDS] and MBCCSR
n
[LCKS] provide the application with the required status
information. The internal status information is not visible to the application.
Table 26-100. Receive Message Buffer Access Region Description
Region
Access from
Region used for
Application
Module
CFG
read/write
—
Message Buffer Configuration, Message Data and Status Access
MSG
read/write
—
Message Data, Header, and Status Access
RX
—
write-only
Message Reception and Status Update
SR
—
read-only
Message Buffer Search Data
Message Buffer Data Field: DATA[0-N]
Message Buffer Header Field: Frame Header
MBCCSRn[DVAL/DUP]
Message Buffer Header Field: Slot Status
Message Buffer Header Field: Data Field Offset
MBCCFRn[CHA/CHB/CCF*]
MBFIDRn[FID]
MBIDXRn[MBIDX]
MBCCSRn[MTD]
RX
SR
CFG
MSG
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...