NXP Semiconductors PXN2020, Reference Manual, Page: 701 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-87
Figure 26-108. Example of FlexRay Memory Layout (MCR[FAM] = 1)
26.6.4.3 Message Buffer Header Area (MCR[FAM] = 0)
The message buffer header area contains all message buffer header fields of the physical message buffers
for all message buffer types. The following rules apply to the message buffer header fields for the three
type of message buffers.
1. The start byte address SADR_MBHF of each message buffer header field for individual message
buffers and receive shadow buffers must fulfill Equation 26-7 .
SADR_MBHF = (i * 10) + SYMBADR[SMBA]; (0 < i < 256) Eqn. 26-7
2. The start byte address SADR_MBHF of each message buffer header field for the FIFO must fulfill
Equation 26-8 .
SADR_MBHF = (i * 10) + SYMDARD[SMBA]; (0 < i < 1024) Eqn. 26-8
FIF
O
H
eader Area
F
IFO
Fl
ex
R
a
y Me
mo
ry
Data Field Offset Frame Header Slot Status
Data Field Offset Frame Header Slot Status
Message Buffer Header Fields
Receive FIFO A
Data Field Offset Frame Header Slot Status
Data Field Offset Frame Header Slot Status
Message Buffer Header Fields
Receive FIFO B
RFSYMBADR[SMBA]
System Memory
Messag
e Buffer H
eader Area
F
lex
R
a
y Me
mor
y
Message Buffer Data Area
Sync Frame Table Area
Data Field Offset Frame Header Slot Status
Data Field Offset Frame Header Slot Status
Message Buffer Header Fields
Individual Message Buffers
Receive Shadow Buffers
Data Field Offset Frame Header Slot Status
10 bytes
SYMBADR[SMBA]
FIFO Message Buffer Data Area