NXP Semiconductors PXN2020, Reference Manual, Page: 645 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-31
26.5.2.17 Channel A Status Error Counter Register (CASERCR)
This register provides the channel status error counter for channel A. The protocol engine generates a slot
status vector for each static slot, each dynamic slot, the symbol window, and the NIT. The slot status vector
contains the four protocol related error indicator bits
vSS!SyntaxError, vSS!ContentError, vSS!BViolation ,
and vSS!TxConflict . The controller increments the status error counter by 1 if, for a slot or segment, at least
one error indicator bit is set to 1. The counter wraps around after it has reached the maximum value. For
more information on slot status monitoring, see
Section 26.6.18, Slot Status Monitoring.
26.5.2.18 Channel B Status Error Counter Register (CBSERCR)
This register provides the channel status error counter for channel B. The protocol engine generates a slot
status vector for each static slot, each dynamic slot, the symbol window, and the NIT. The slot status vector
contains the four protocol related error indicator bits
vSS!SyntaxError , vSS!ContentError , vSS!BViolation ,
and vSS!TxConflict . The controller increments the status error counter by 1 if, for a slot or segment, at least
Table 26-22. MBIVEC Field Descriptions
Field Description
TBIVEC Transmit Buffer Interrupt Vector — This field provides the number of the lowest numbered enabled transmit
message buffer that has its interrupt status flag MBIF and its interrupt enable bit MBIE set. If there is no transmit
message buffer with the interrupt status flag MBIF and the interrupt enable MBIE bits asserted, the value in this
field is set to 0.
RBIVEC Receive Buffer Interrupt Vector — This field provides the message buffer number of the lowest numbered
receive message buffer which has its interrupt flag MBIF and its interrupt enable bit MBIE asserted. If there is
no receive message buffer with the interrupt status flag MBIF and the interrupt enable MBIE bits asserted, the
value in this field is set to 0.
Base + 0x0024 Additional Reset: RUN Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R STATUS_ERR_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-17. Channel A Status Error Counter Register (CASERCR)
Table 26-23. CASERCR Field Descriptions
Field Description
STATUS_ERR_CNT Channel Status Error Counter — This field provides the current value channel status error counter. The
counter value is updated within the first macrotick of the following slot or segment.
Base + 0x0026 Additional Reset: RUN Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R STATUS_ERR_CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-18. Channel B Status Error Counter Register (CBSERCR)