NXP Semiconductors PXN2020, Reference Manual, Page: 556 / 1376

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
24-36 Freescale Semiconductor
Figure 24-22. Example of Multiple Loop Iterations
Figure 24-23 lists the memory array terms and how the TCD settings interrelate.
Figure 24-23. Memory Array Terms
24.5.2 DMA Programming Errors
The DMA performs various tests on the transfer control descriptor to verify consistency in the descriptor
data. Most programming errors are reported on a per-channel basis with the exception of two errors:
group-priority error and channel-priority error, or EDMA_ESR[GPE] and EDMA_ESR[CPE],
respectively.
For all error types other than group- or channel-priority errors, the channel number causing the error is
recorded in the EDMA_ESR. If the error source is not removed before the next activation of the problem
channel, the error is detected and recorded again.
DMA request
Minor loop 3
Current major loop
iteration count
(CITER)
Example memory array
•
•
•
DMA request
Minor loop 2
•
•
•
DMA request
Minor loop 1
•
•
•
Major loop
xADDR:
(Starting address)
xSIZE:
(Size of one data
Minor loop
(NBYTES in
minor loop, often
the same value
as xSIZE)
Offset (xOFF): Number of
bytes added to current
address after each transfer
(Often the same value
as xSIZE)
•
Minor loop
Each DMA source (S) and
destination (D) has its own:
• Address (xADDR)
• Size (xSIZE)
• Offset (xOFF)
xLAST: Number of bytes
added to current address
Peripheral queues typically
have size and offset
equal to NBYTES
•
•
after major loop
(typically used to
loop back)
transfer)
•
•
•
•
•
•
Last minor loop
• Modulo (xMOD)
• Last address adjustment
(xLAST) where x = S or D
•
•
•