NXP Semiconductors PXN2020, Reference Manual, Page: 471 / 1376

Error Correction Status Module (ECSM)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 19-11
ECC event in the platform flash causes the address, attributes and data associated with the access to be
loaded into the PFEAR, PFEMR, PFEAT, and PFEDR registers and also the appropriate flag (PF1BC or
PFNCE) in the ECC status register to be asserted.
This register is read-only; any attempted write is ignored. See Figure 19-7 and Table 19-9 for the platform
flash ECC attributes register definition.
19.2.2.8 Platform Flash ECC Data Register (PFEDR)
The PFEDR is a 64-bit register for capturing the data associated with the last properly enabled ECC event
in the platform flash memory. Depending on the state of the ECC configuration register, an ECC event in
the platform flash causes the address, attributes and data associated with the access to be loaded into the
PFEAR, PFEMR, PFEAT, and PFEDR registers and also the appropriate flag (PF1BC or PFNCE) in the
ECC status register to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register is read-only; any attempted write is ignored. See Figure 19-9 and Table 19-10 for the platform
flash ECC data register definition.
Offset: ECSM_BAS 0x0057 Access: User read-only
0 1 2 3 4 5 6 7
R WRITE SIZE PROTECTION
W
Reset U U U U U U U U
Figure 19-7. Platform Flash ECC Attributes (PFEAT) Register
Table 19-9. PFEAT Field Descriptions
Field Description
WRITE 0 Read access.
1 Write access.
SIZE 000 8-bit access
001 16-bit access
010 32-bit access
011 64-bit access
1xx Reserved
PROTEC
TION
Cache:
0xxx Non-cacheable
1xxx Cacheable
Buffer:
x0xx Non-bufferable
x1xx Bufferable
Mode:
xx0x User mode
xx1x Supervisor mode
Type:
xxx0 I-Fetch
xxx1 Data