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PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 15-1
Chapter 15
Semaphores
15.1 Introduction
In a dual processor chip, semaphores are used to let each processor know who has control of common
memory. Before a core can update or read memory coherently, it has to check the semaphore to see if the
other core is not already updating the memory. If the semaphore is clear, it can write common memory, but
if it is set, it has to wait for the other core to finish and clear the semaphore.
The semaphores module provides the hardware support needed in multi-core systems for implementing
semaphores and provide a simple mechanism to achieve lock/unlock operations via a single write access.
This approach eliminates architecture-specific implementations like atomic (indivisible)
read-modify-write instructions or reservation mechanisms. The result is an architecture-neutral solution
that provides hardware-enforced gates as well as other useful system functions related to the gating
mechanisms.
15.1.1 Block Diagram
Figure 15-1 is a simplified block diagram of the semaphores module that illustrates the functionality and
interdependence of major blocks. In the diagram, the register blocks named gate0, gate1, ..., gate 15
include the finite state machines implementing the semaphore gates plus the interrupt notification logic.