Semaphores
PXN20 Microcontroller Reference Manual, Rev. 1
15-2
Freescale Semiconductor
Figure 15-1. Semaphores Block Diagram
15.1.2
Features
The semaphores module implements hardware-enforced semaphores as a peripheral device and has these
major features:
•
Support for 16 hardware-enforced gates in a dual-processor configuration
— Each hardware gate appears as a three-state, 2-bit state machine, with all 16 gates mapped as
an array of bytes
– Three-state implementation
if gate = 0b00, then state = unlocked
ips_wdata
ips_addr
decode
mux
IPS Bus
31
0
control
ips_rdata
31
0
aips_master
2
0
=
=
master_eq_cp{0,1}
gate0
gate1
gate2
gate3
gate12
gate13 gate14 gate15
=
=
wdata_eq_{unlock, cp[0-1]_lock}
=
cp0_semaphore_int
cp1_semaphore_int
Summary of Contents for PXN2020
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