NXP Semiconductors PXN2020, Reference Manual, Page: 410 / 1376

e200z0 Core (Z0)
PXN20 Microcontroller Reference Manual, Rev. 1
14-12 Freescale Semiconductor
Table 14-4 summarizes the e200z0 interrupts. Each ISR begins at a fixed offset as defined below.
AP unavailable IVOR 9 Unused
Decrementer IVOR 10 Unused
Fixed Interval
Timer
IVOR 11 Unused
Watchdog Timer IVOR 12 Unused
Data TLB Error IVOR 13 Unused
Instruction TLB
Error
IVOR 14 Unused
Debug IVOR 15
Trap, Instruction Address Compare, Data Address Compare, Instruction
Complete, Branch Taken, Return from Interrupt, Interrupt Taken, External
Debug Event, Unconditional Debug Event
Reserved IVOR 16-31 —
1
Autovectored External and Critical Input interrupts use this IVOR. Vectored interrupts supply an interrupt vector offset directly.
Table 14-4. e200z0 Interrupts
IRQ # Offset Size [Byte] Resource
— 0x0000 16 Critical Input (NMI)
— 0x0010 16 Machine check
— 0x0020 16 Data Storage
— 0x0030 16 Instruction Storage
— 0x0040 16 External Input (INTC software vector mode)
— 0x0050 16 Alignment
— 0x0060 16 Program
— 0x0070 16 Reserved
— 0x0080 16 System call
— 0x0090 96 Unused
— 0x00F0 16 Debug
— 0x0100 1792 Unused
Table 14-3. Exceptions and Conditions (continued)
Interrupt Type
Interrupt Vector
Offset Register
Causing Conditions