NXP Semiconductors PXN2020, Reference Manual, Page: 382 / 1376

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
13-18 Freescale Semiconductor
13.3.1.5.1 MAS[0] Register
The MAS[0] register is shown in Figure 13-7 .
MAS[0] fields are defined in Table 13-4 .
13.3.1.5.2 MAS[1] Register
The MAS[1] register is shown in Figure 13-8 .
MAS[1] fields are defined in Table 13-5 .
SPR: 624 Access: Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
— TLBSEL — ESEL — NV
W
Reset Undefined on Power Up

Unchanged on Reset
Figure 13-7. MAS Register 0 Format—MAS[0]
Table 13-4. MAS[0]—MMU Read/Write and Replacement Control
Field Description
TLBSEL Selects TLB for access.
01 TLB1 (ignored by the e200z6, write to 01 for future compatibility)
ESEL Entry select for TLB1.
NV Next replacement victim for TLB1 (software managed). Software updates this field; it is copied to the ESEL field on
a TLB error.
SPR: 625 Access: Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
VALID IPROT — TD — TS TSIZE —
W
Reset Undefined on Power Up

Unchanged on Reset
Figure 13-8. MMU Assist Register 1—MAS[1]
Table 13-5. MAS[1]—Descriptor Context and Configuration Control
Field Description
VALID TLB entry valid.
0 This TLB entry is invalid.
1 This TLB entry is valid.
IPROT Invalidation protect
0 Entry is not protected from invalidation.
1 Entry is protected from invalidation.
Protects TLB entry from invalidation by tlbivax (TLB1 only), or flash invalidates through MMUCSR0[TLB1_FI].
TID Translation ID bits.
This field is compared with the current process IDs of the effective address to be translated. A TID value of 0 defines
an entry as global and matches with all process IDs.