NXP Semiconductors PXN2020, Reference Manual, Page: 379 / 1376

e200z6 Core (Z6)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 13-15
13.3.1.1 Translation Lookaside Buffer (TLB)
The TLB consists of a 32-entry, fully associative content addressable memory (CAM) array. To perform a
lookup, the CAM is searched in parallel for a matching TLB entry. The contents of this TLB entry are then
concatenated with the page offset of the original effective address. The result constitutes the physical
address of the access.
Table 13-3 shows the TLB entry bit definitions.
The TLB is accessed indirectly through several MMU assist (MAS) registers. Software can read and write
to the MMU assist registers with
mtspr (move to SPR) and mfspr (move from SPR) instructions. The
MMU registers contain information related to reading and writing an entry in the TLB. Data is read from
the TLB into the MAS registers with a
tlbre (TLB read entry) instruction. Data is written to the TLB from
the MAS registers with a tlbwe (TLB write entry) instruction.
Refer to Section 13.3.1.5, MMU Assist Registers (MAS[0:4], MAS[6]), and the
e200z6 PowerPC
TM
Core Reference Manual for more details.
13.3.1.2 Translation Flow
The effective address, concatenated with the address space value of the MSR bit (MSR[IS] or MSR[DS]),
is compared to the number of bits of the EPN field and the TS field of TLB entries. If the contents of the
effective address plus the address space bit matches the EPN field and TS bit of the TLB entry, that TLB
entry is a candidate for a possible translation match. In addition to a match in the EPN field and TS, a
matching TLB entry must match with the current process ID of the access (in PID0), or have a TID value
of 0, indicating the entry is globally shared among all processes.
Figure 13-4 shows the translation match logic for the effective address plus its attributes, collectively
called the virtual address, and how it is compared with the corresponding fields in the TLB entries.
Table 13-3. TLB Entry Bit Definitions
Field Comments
V Valid bit for entry
TS Translation address space (compared against AS bit)
TID[0:7] Translation ID (compared against PID0 or ‘0’)
EPN[0:19] Effective page number (compared against effective address)
RPN[0:19] Real page number (translated address)
SIZE[0:3] Page size = 4 KB,16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MB
SX, SW, SR Supervisor execute, write, and read permission bits
UX, UW, UR User execute, write, and read permission bits
WIMGE Translation attributes (Write-through required, cache-inhibited, memory coherence required, guarded, endian)
U0–U3 User bits—used by software only
IPROT Invalidation protect
VLE VLE page indicator