NXP Semiconductors PXN2020, Reference Manual, Page: 336 / 1376

Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
12-10 Freescale Semiconductor
Because the MCR[DONE] flag can be set too soon, a delay needs to be
inserted between setting the MCR[ESUS] or MCR[PSUS] and reading the
same flash partition. The minimum duration of the delay should be 40 us to
guarantee correct operation.
12.3.2.1.1 MCR Simultaneous Register Writes
A number of MCR bits are protected against write when another bit, or set of bits, is in a specific state.
These write locks are covered on a bit by bit basis in the preceding section. The write locks detailed in the
previous section do not consider the effects of trying to write two or more bits simultaneously. The effects
of writing bits simultaneously which put the module in an illegal state are detailed here.
The flash module does not allow the user to write bits simultaneously which put the device into an illegal
state. This is implemented through a priority mechanism among the bits. The bit changing priorities are
detailed in
Table 12-4 .
If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority
level is written. Setting two bits with the same priority level is prevented by existing write locks or do not
put the flash in an illegal state.
For example, setting ERS and PGM simultaneously results in only ERS being set. Attempting to clear
EHV while setting PSUS results in EHV being cleared, while PSUS is unaffected.
12.3.2.2 Low/Mid Address Space Block Locking Register (LML)
The Low/Mid Address Block Locking Register (LML) provides a means to protect blocks from being
modified. These bits, along with bits in the Secondary LLOCK (SLL), determine if the block is locked
from program or erase. An “OR” of LML and SLL determine the final lock status.
NOTE
A reset value of 1* in Figure 12-4 indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
The LML register is shown in Figure 12-4 and Table 12-5 .
Table 12-4. MCR Bit Set/Clear Priority Levels
Priority Level MCR Bit(s)
1 ERS
2 PGM
3 EHV
4 ESUS, PSUS