NXP Semiconductors PXN2020, Reference Manual, Page: 1252 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-102 Freescale Semiconductor
36.7.9.7.2 JTAG Sequence for Read Access of Memory-Mapped Resources
36.7.9.7.3 JTAG Sequence for Write Access of Memory-Mapped Resources
36.8 Debug Implementation
This section describes the practical implementation of the debug port, its management, and the
multiplexing strategy of its pads.
Standard JTAG (compliant to IEEE 1149.1) support is provided on all versions of the PXN20, and is
described in
Chapter 35, IEEE 1149.1 Test Access Port Controller (JTAGC). The Nexus Debug Interface
(NDI), which is composed of the (N2+) and Nexus3 (N3) clients running on the two cores, is
available on the 256-pin package. This provides real-time development capabilities in compliance with the
IEEE-ISTO 5001-2003 standard.
36.9 Debug Capabilities
The debug classifications according to the Nexus consortium are shown in Figure 36-80 .
Table 36-66. Accessing Memory-Mapped Resources (Reads)
Step # TCLK clocks Description
1 13 Nexus Command = write to read/write access address register (RWA)
2 37 Write RWA (initialize starting read address—data input on TDI)
3 13 Nexus Command = write to read/write control/status register (RWCS)
4 37 Write RWCS (initialize read access mode and CNT value—data input on TDI)
5 13 Nexus Command = read read/write access data register (RWD)
6 37 Read RWD (data output on TDO)
7 — If CNT > 0, go back to Step #5
Table 36-67. Accessing Memory-Mapped Resources (Writes)
Step # TCLK clocks Description
1 13 Nexus Command = write to read/write access control/status register (RWCS)
2 37 Write RWCS (initialize write access mode and CNT value—data input on TDI)
3 13 Nexus Command = write to read/write address register (RWA)
4 37 Write RWA (initialize starting write address—data input on TDI)
5 13 Nexus Command = read read/write access data register (RWD)
6 37 Write RWD (data output on TDO)
7 — If CNT > 0, go back to Step #5