NXP Semiconductors PXN2020, Reference Manual, Page: 1135 / 1376

PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 35-1
Chapter 35
IEEE 1149.1 Test Access Port Controller (JTAGC)
35.1 Introduction
The JTAGC provides the means to test chip functionality and connectivity and controls access to the debug
features of the device while remaining transparent to system logic when not in test mode. Testing is
performed via a boundary scan technique, as defined in the IEEE

1149.1-2001 standard. Instructions can
be executed that allow the test access port (TAP) to be shared with other modules on the MCU. All data
input to and output from the JTAGC is communicated in serial format.
Chapter 36, Nexus Development Interface (NDI), includes information relevant to use of the JTAGC,
including Section 35.6, Initialization/Application Information, which gives practical application examples
for both controllers.
35.1.1 Block Diagram
A simplified block diagram of the JTAGC illustrates the functionality and interdependence of major blocks
(see
Figure 35-1 ). The JTAG port of the device consists of four inputs and one output. These pins include
JTAG compliance select (JCOMP), test data input (TDI), test data output (TDO), test mode select (TMS),
and test clock input (TCK). TDI, TDO, TMS, and TCK are compliant with the IEEE 1149.1-2001 standard
and are shared with the NDI through the test access port (TAP) interface.