NXP Semiconductors PXN2020, Reference Manual, Page: 1149 / 1376

IEEE 1149.1 Test Access Port Controller (JTAGC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 35-15
35.6 Initialization/Application Information
The test logic is a static logic design, and TCK can be stopped in either a high or low state without loss of
data. However, the system clock is not synchronized to TCK internally. Any mixed operation using both
the test logic and the system functional logic requires external synchronization.
To initialize the JTAGC module and enable access to registers, the following sequence is required:
1. Set the JCOMP signal to logic 1, thereby enabling the JTAGC TAP controller.
2. Load the appropriate instruction for the test or action to be performed.
011 0100 Debug Control Register 3 (DBCR3)
2
011 0101 – 110 1111 Reserved (do not access)
111 0000 – 111 1001 General Purpose Register Selects [0:9]
111 1010 Cache Debug Access Control Register (CDACNTL)
1
111 1011 Cache Debug Access Data Register (CDADATA)
1
111 1100 – 111 1011 Reserved
111 1100 Nexus Access
111 1101 LSRL Select
(factory test use only)
111 1110 Enable_OnCE
111 1111 Bypass
1
Reserved, not implemented on e200z0.
2
Reserved, not implemented on e200z0. Do not access.
Table 35-3. e200z0 and e200z6 OnCE Register Addressing (continued)
RS Register Selected