NXP Semiconductors PXN2020, Reference Manual, Page: 1232 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-82 Freescale Semiconductor
NOTE
The WT bits control program trace only if the TM bits in the development
control register 1 (DC1) have not already been set to enable program trace.
36.7.8 Register Access via JTAG / OnCE
Access to register resources is enabled by loading a single instruction
(ACCESS_AUX_TAP_Z0) into the JTAGC instruction register (IR), and then loading the corresponding
OnCE OCMD register with the NEXUS2_ACCESS instruction (refer to
Table 36-2 ). For the
module, the OCMD value is 0b00_0111_1100.
Once the ACCESS_AUX_TAP_Z0 instruction has been loaded, the JTAG/OnCE port allows tool/target
communications with all registers according to the register map in
Table 36-48 .
Reading/writing of a register then requires two (2) passes through the data-scan (DR) path of the
JTAG state machine (see 36.6.10.8).
1. The first pass through the DR selects the register to be accessed by providing an index
(see Table 36-48 ), and the direction (read/write). This is achieved by loading an 8-bit value into the
JTAG data register (DR). This register has the following format:
Table 36-56. WT Field Descriptions
Field Description
PTS[2:0] Program trace start control.
000 Trigger disabled
001 Use watchpoint #0 (IAC1 from Nexus1)
010 Use watchpoint #1 (IAC2 from Nexus1)
011 Use watchpoint #2 (IAC3 from Nexus1)
100 Use watchpoint #3 (IAC4 from Nexus1)
101 Use watchpoint #4 (DAC1 from Nexus1)
110 Use watchpoint #5 (DAC2 from Nexus1)
111 Reserved
PTE[2:0] Program trace end control.
000 Trigger disabled
001 Use watchpoint #0 (IAC1 from Nexus1)
010 Use watchpoint #1 (IAC2 from Nexus1)
011 Use watchpoint #2 (IAC3 from Nexus1)
100 Use watchpoint #3 (IAC4 from Nexus1)
101 Use watchpoint #4 (DAC1 from Nexus1)
110 Use watchpoint #5 (DAC2 from Nexus1)
111 Reserved
Nexus Register Index
(7 bits) (1 bit)
R/W
RESET Value: 0x00