NXP Semiconductors PXN2020, Reference Manual, Page: 1226 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-76 Freescale Semiconductor
36.7.7 Register Definition
36.7.7.1 Development Control Register 1, 2 (DC1, DC2)
The development control registers are used to control the basic development features of the
module. Development control register 1 is shown in
Figure 36-53 and its fields are described in
Table 36-49 .
Nexus Reg: 0x2 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OPC MCK_DIV
EOC
0
PTM WEN
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
OVC EIC TM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-53. Development Control Register 1 (DC1)
Table 36-49. DC1 Field Descriptions
Field Description
OPC
1
Output port mode control.
0 Reduced-port mode configuration (not available on the PXN20)
1 Full-port mode configuration (12 MDO pins)
MCK_DIV [1:0]
1
MCKO clock divide ratio (see note below).
00 MCKO is 1x processor clock freq.
01 MCKO is 1/2x processor clock freq.
10 MCKO is 1/4x processor clock freq.
11 MCKO is 1/8x processor clock freq.
EOC[1:0] EVTO control.
00 EVTO upon occurrence of watchpoints (configured in DC2)
01 EVTO upon entry into debug mode
10 EVTO upon timestamping event
11 Reserved
PTM Program trace method.
0 Program trace uses traditional branch messages
1 Program trace uses branch history messages
WEN Watchpoint trace enable.
0 Watchpoint Messaging disabled
1 Watchpoint Messaging enabled