Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-58
Freescale Semiconductor
Exception conditions that result in data trace synchronization are summarized in
.
36.6.10.4.3
DTM Operation
DTM Queueing
implements a message queue for DTM messages. Messages that enter the queue are transmitted
via the auxiliary pins in the order in which they are queued.
NOTE
If multiple trace messages need to be queued at the same time, watchpoint
messages have the highest priority (WPM
OTM
BTM
DTM).
Relative Addressing
The relative address feature is compliant with the IEEE-ISTO 5001-2003 standard recommendations, and
is designed to reduce the number of bits transmitted for addresses of data trace messages. Refer to
for details.
Table 36-35. Data Trace Exception Summary
Exception Condition
Exception Handling
System Reset Negation
At the negation of JTAG reset (JCOMP), queue pointers, counters, state machines, and registers
within the module are reset. If data trace is enabled, the first data trace message is a
data write/read with sync. message.
Data Trace Enabled
The first data trace message (after data trace has been enabled) is a synchronization message.
Exit from Low Power/Debug Upon exit from a low power mode or debug mode, the next data trace message is converted to a
data write/read with sync. message.
Queue Overrun
An error message occurs when a new message cannot be queued due to the message queue
being full. The FIFO discards messages until it has completely emptied the queue. Once emptied,
an error message is queued. The error encoding indicates which types of messages attempted
to be queued while the FIFO was being emptied. The next DTM message in the queue is a data
write/read with sync. message.
Periodic Data Trace Sync.
A forced synchronization occurs periodically after 255 data trace messages have been queued.
A data write/read with sync. message is queued. The periodic data trace message counter then
resets.
Event In
If the Nexus module is enabled, a EVTI assertion initiates a data trace write/read with sync.
message upon the next data write/read (if data trace is enabled and the EIC bits of the DC1
register have enabled this feature).
Attempted Access to Secure
Memory
For devices that implement security, any attempted read or write to secure memory locations
temporarily disables data trace and causes the corresponding DTM to be lost. A subsequent
read/write queues a data trace read/write with sync. message.
Collision Priority
All messages have the following priority: WPM
OTM
BTM
DTM. A DTM message that
attempts to enter the queue at the same time as a watchpoint message or ownership trace
message or branch trace message is lost. A subsequent read/write queues a data trace
read/write with sync. message.
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
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Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
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