NXP Semiconductors PXN2020, Reference Manual, Page: 1185 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-35
36.6.8.3 Read/Write Access Control/Status (RWCS)
The read write access control/status register provides control for read/write access. Read/write access
provides DMA-like access to memory-mapped resources on the system bus while the processor is halted
or during runtime. The RWCS register is shown in
Figure 36-17 and its fields are described in Table 36-23 .
The RWCS register also provides read/write access status information as shown in Table 36-24 .
LPC CPU Low-Power Mode Status.
00 Normal (run) mode.
01 CPU in halted state.
10 CPU in stopped state.
11 Reserved.
CHK CPU Checkstop Status.
0 CPU not in checkstop state.
1 CPU in checkstop state.
Nexus Reg: 0x7 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
AC RW SZ MAP PR BST
0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CNT ERR DV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-17. Read/Write Access Control/Status Register (RWCS)
Table 36-23. RWCS Field Description
Field Description
AC Access Control.
0 End access.
1 Start access.
RW Read/Write Select.
0 Read access.
1 Write access.
SZ Word Size.
000 8-bit (byte.)
001 16-bit (halfword).
010 32-bit (word).
011 64-bit (doubleword—only in burst mode).
100–111 Reserved (default to word).
Table 36-22. DS Field Descriptions (continued)
Field Description