NXP Semiconductors PXN2020, Reference Manual, Page: 1182 / 1376

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-32 Freescale Semiconductor
36.6.8 Register Definition
36.6.8.1 Development Control Register 1, 2 (DC1, DC2)
The development control registers are used to control the basic development features of the Nexus module.
Figure 36-14 shows DC1 and Table 36-20 describes the register’s fields.
0xB WT Watchpoint trigger 0x16 0x17
0xD DTC Data trace control 0x1A 0x1B
0xE DTSA1 Data trace start address 1 0x1C 0x1D
0xF DTSA2 Data trace start address 2 0x1E 0x1F
0x12 DTEA1 Data trace end address 1 0x24 0x25
0x13 DTEA2 Data trace end address 2 0x26 0x27
0x14 -> 0x3F — Reserved 0x28->0x7E 0x29->0x7F
Nexus Reg: 0x02 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OPC MCK_DIV
EOC
0
PTM WEN
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0
OVC EIC TM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 36-14. Development Control Register 1 (DC1)
Table 36-20. DC1 Field Descriptions
Field Description
OPC
1
Output Port Mode Control.
0 Reduced-port mode configuration (4 MDO pins).
1 Full-port mode configuration (8 MDO pins).
MCK_DIV
1
MCKO Clock Divide Ratio (see note below).
00 MCKO is 1x processor clock freq.
01 MCKO is 1/2x processor clock freq.
10 MCKO is 1/4x processor clock freq.
11 MCKO is 1/8x processor clock freq.
Table 36-19. Memory Map (continued)
Access
Opcode
Register Name Register Description Read Address Write Address