NXP Semiconductors PXN2020, Reference Manual, Page: 1076 / 1376

Cross Triggering Unit (CTU)
PXN20 Microcontroller Reference Manual, Rev. 1
33-8 Freescale Semiconductor
Figure 33-3. CTU Trigger Sources Allocation
All the flags can be divided in to four different counter groups which signify which PWM channel clock
group the particular event is generated. The four counters can run in parallel and the trigger output is
generated for the counter expiring first. If more than one counter reaches zero at the same time, the lower
index counter has higher priority and the corresponding channel value is provided to the ADC.
Each trigger input from the CTU is connected to the Event Trigger signal of an eMIOS or PIT channel.
The assignment between eMIOS/PIT outputs and CTU trigger inputs is defined in
Table 33-9 .
The eMIOS signal “FLAG” is used in DMA mode to interface with the trigger input of the CTU. The CTU
resets the FLAG signal once the ADC conversion request has been completed.
NOTE
The eMIOS channels can either be used with eDMA or CTU. They cannot
be used with eDMA and CTU at the same time.
Table 33-9. CTU Trigger Sources
Trigger Number Module Source
0 eMIOS Channel_0
1 eMIOS Channel_1
2 eMIOS Channel_2
3 eMIOS Channel_3
4 eMIOS Channel_4
5 eMIOS Channel_5
6 eMIOS Channel_6
7 eMIOS Channel_7
8 eMIOS Channel_8
Event Configuration Register_0
Trigger Inputs
Trig_0
Event Configuration Register_1
Trig_1
Event Configuration Register_31
Trig_31
Event Configuration Register_32
Trig_32
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