NXP Semiconductors PXN2020, Reference Manual, Page: 1035 / 1376

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-45
NOTE
If the eSCI module enters stop while the transmit DMA is enabled and
messages are being transmitted, when the CPU exits stop or doze mode, it
is possible that DMA requests will not be generated by the eSCI module. To
avoid this, the application should ensure that the eSCI module is idle before
entering the stop mode. The eSCI module is idle when both transmitter and
receiver active status bits in the Interrupt Flag and Status Register 1
(eSCI_IFSR1) are not set. The application should not trigger a new
transmission on the eSCI module if the application is preparing for the stop
mode.
31.4.6.3.2 DMA Controlled LIN TX Frame Generation
In this mode, the eSCI module handles the generation of an LIN TX Frame internally. When new data is
ready for transmission, the module generates the transmit DMA request and the DMA controller delivers
the required data. The application requests the eSCI module to enter this mode by setting the TXDMA bit
in the eSCI Control Register 2 (eSCI_CR2). From this point in time, the module starts the generation of
DMA requests and frame transmission. Before entering this mode, the application should perform the
following actions:
1. Configure the module for LIN mode.
2. Enable the transmitter by setting TE in eSCI Control Register 1 (eSCI_CR1) to 1.
3. Set up the DMA controller channel and provide frame data in system memory.
Figure 31-40 shows an overview of the DMA-controlled LIN TX frame. The content of the fields in the
memory is the same as described in eSCI LIN Transmit Register (eSCI_LTR) — LIN TX Frame
Generation.
Figure 31-40. DMA Controlled LIN TX Frame Generation
DMA
Controller
eSCI
CSM
TX DMA
channel
ID[5:0] P[1:0]
LEN
1
CSE CRC TD
2
0
DATA 1
DATA 2
DATA N
System Memory
1
LEN must be set to N
2
TD must be set to 1
Break Synch Identifier DATA 1 DATA N Checksum
LIN TX frame