NXP Semiconductors PTN3460, User Manual, Page: 9 / 15

UM10492 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
User manual Rev. 1.1 — 16 March 2015 9 of 14
NXP Semiconductors
UM10492
PTN3460 eDP to LVDS bridge IC application board
5. Connector specifications
5.1 Connectors
5.2 Cables
5.3 Jumpers
Table 1. Connectors
Connector Type Supplier Part number
J1 DP CONN SINK conn-47272-0001 Molex 47272-0001
J2 FI-X30SSL-HF conn_FI-X30SSL-HF JAE FI-X30SSL-HF
J3, J5 HEADER 4 hdr_4x1 Sullins PBC04SAAN
J4 HEADER, 2

5 hdr_5x2 Sullins PBC05DAAN
J6, J8 SOFT TOUCH CONN ES387-68701 conn_ES387-68701 Agilent ES387-68701
J7 FI-XB30SRL-HF11 conn_FI-XB30SRL-HF11 JAE FI-XB30SRL-HF11
J9 MOLEX ATX PWR PN 39-29-9202 cn_molex_minfit20p_vt Molex 39-29-9202
CN1 S8B-PH-SM4-TB(LF)(SN) conn_8x1_2mm JST Sales S8B-PH-SM4-TB(LF)(SN)
Table 2. Cables
Test cable location Test cable Description
J1 DP 1.1 cable Purchase ready-made cable
J2 iMac 30-position eDP 1 mm cable Made from LVDS 30-position cable kit
J3, J5 I
2
C Bird 1

4 cable Ready-made with I
2
C Bird box
J4 JTAG 2

5 ribbon cable Ready-made with FS2 box
J6, J8 Agilent soft-touch probes 90-pin differential probe E5387A (2)
J7 AUO 30-position LVDS 1 mm cable Made from LVDS 30-position cable kit
J9 Backlight inverter 1

8 Made from accessories
Table 3. Jumpers
Jumper
number Signal names Jumper settings Default
setting
JP1 U1 MUX
GPU_SEL 1-2 HIGH — select DP inputs
2-3 LOW — select eDP inputs
1-2
JP2 U1 MUX
AUX_SEL 1-2 HIGH — select AUX from DP inputs
2-3 LOW — select AUX from eDP inputs
1-2
JP3 1V8_PTN 1-2 — 1.8 V from on-board regulator
2-3 — 1.8 V from Buck converter
1-2
JP4 TESTMODE 1-2 HIGH — CFG[4:1] = JTAG pins
2-3 LOW — CFG[4:1] = CONFIG pins
2-3
JP5 DEV_CFG 1-2 HIGH — I
2
C-bus master
open — I
2
C-bus slave (0C0h)
2-3 LOW — I
2
C-bus slave (040h)
2-3