NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
278 of 345
14.3.3.9
Data sampling
Basically, the RX sampler will detect a falling edge on HSU_RX input signal,
resynchronize it to sampling clock, then will start counting a number of sample clock
cycles before sampling each data bit. The RX data sampling is based on the ratio
between the sampling clock (27.12 MHz) and the communication baud rate: integer part
of this ratio is stored in HSU_RX_DIVIDER, and the decimal part of this ratio will be
reflected in HSU_RX_CORRECT, by distributing ‘1’ in this register with a proportion
equivalent to the decimal part of the ratio. The RX sampler will count up to this value to
determine the bit length. The sampled time (ideally at the middle of bit length) is
determined as HSU_RX_DIVIDER/2 (this is an integer). When the ratio between the
sampling clock frequency and the baud rate is not an integer, then HSU_RX_CORRECT
provides a mean to extend individually the duration of each sampled bit of one sample
clock cycle: the proportion of ‘1’ in this register should reflect the decimal part of the ratio
between sampling clock and baud rate. At start bit detection, the counter starts with value
3 to compensate for the start bit detection and re synchronization which consumed 2 to 3
clock cycles (not deterministic due to asynchronicity between RX and sampling clock).
Due to clock uncertainty given by start bit detection, average sample time for first bit is
HSU_RX_DIVIDER/2+0.5 clock cycles when HSU_RX_DIVIDER is even, and
HSU_RX_DIVIDER/2 clock cycles when HSU_RX_DIVIDER is odd.
shows the
duration of each sampled bit. If we only consider 1 stop bit, and we call the number of ‘1’
in RX_correct[9:0], we can compute the average bit duration:
(RX_d/10+0.05)xsample_clock_period. This is why d should approximately
reflect the decimal part of sample_clock_frequency/baud rate.
Table 318.
Bit duration in sample clock cycle
Bit
Duration (# of sample clock cycles)
Start bit
RX_0.5+RX correct[0]
Bit 0
RX_RX_correct[1]
Bit 1
RX_RX_correct[2]
Bit 2
RX_RX_correct[3]
Bit 3
RX_RX_correct[4]
Bit 4
RX_RX_correc[5]
Bit 5
RX_RX_correct[6]
Bit 6
RX_RX_correct[7]
Bit 7
RX_RX_correct[8]
Stop Bit 0
RX_RX_correct[9]
Stop Bit 1
RX_RX_correct[10]
As a conclusion, RX_DIVIDER will be programmed to the integer part of 27.12/baud rate.
RX_CORRECT will be programmed with an evenly distributed proportion of 1 equal to
the decimal part of this ratio (for example, if ratio if 8.25, then RX_correct will have 1/4 of
‘1’ bits, for example: 01000100). A script is provided which can give one of the best
values for RX_correct (best sampling results for given clock accuracy of both the host
and the hostif).
