NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
276 of 345
14.3.3.6
EOF detection
For HS UART, the EOF is determined by the sampling of EOF_SIZE bits of value one.
To prevent the race condition between EOF detection and retransmission from the host,
an additional time of 5 bits is required before retransmitting the data. The EOF_size
defines the maximum inter-byte duration in a frame, while the E5 defines the
minimum inter-frame duration between 2 frames.
Fig 63. EOF_SIZE: max inter-byte delay and min inter-frame delay
Table 317. EOF duration in us
Bit rate (kBaud)
EOF_SIZE=10
EOF_SIZE=50
EOF_SIZE=100
57.6
174
869
1737
115.2
87
434
869
921.6
11
55
109
1288
8
39
78
3500
2.9
14.3
28.6
3750
2.7
13.4
26.7
4000
2.5
12.5
25
5000
2
10
20
14.3.3.7
Baud rate estimation
In order to be independent of clock ratio between HS UART baud rate and host interface
sample clock, a baud rate estimator was implemented.
The principle of this estimator
is that the host sends a calibration byte of value 0x00 at beginning of each frame.
First transmission from the host interface to the host must occur after previous
reception of such a frame when HSU_BR_ESTIMATOR_MODE is 1 (Hence using
baud rate estimator in automatic mode is not possible if full-duplex HSU is used).
This byte is used to measure sample clock for reception of next bytes and transmission
of next frame. Usage of this baud rate estimator assumes that no important clock
frequency deviation will happen from reception of this first byte until the last byte to be
sent by host interface. Hence, this is well adapted to receive a message and answer to
this message after firmware processing. But if the host interface wants to transmit data
with no prior data reception (or with a long time since prior reception), then clock
frequency may have changed and an accurate clock will be needed.
The baud rate estimator is active when bit HSU_BR_ESTIMATOR_MODE of
HSU_CONTROL_REG is set to 1 or 2. When active, the first received byte must be
0x00, which will be sent as 9 consecutive ‘0’ bits on RX line. Then the number of edges
of sample clock are counted and divided by 9: The result of this division is used to
