NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
17 of 345
•
2.8 ms maximum to write a page on the EEPROM, with a max. power consumption of
2 mA
•
2.5 ms to write a page on the Flash in typical condition
•
1.03 ms to write a page on the Flash with maximum clock speed, with a max. power
consumption of 3 mA
•
Test support Unit with CRC computation of the EEPROM and flash
content
3.2 AHB interface
AMBA 3 AHB Lite slave interface is implemented to connect the CPU to the EECTRL.
The wait states are inserted with individual length for a read or write access.
3.3 Memory map
The memory map for the EECTRL module is divided into four parts:
•
0x0020_0000 - 0x0020_0FFF - EECTRL registers area
•
0x0020_1000 - 0x0020_1FFF - 4 kBytes DATA EEPROM Area
•
0x0020_2000 - 0x0020_2FFF - UNDEFINED area
•
0x0020_3000 - 0x0022_AFFF - 160 kBytes flash area
3.4 EEPROM controller
3.4.1 Write operation
Write operation cannot be handled within one AHB clock cycle, therefore wait states are
inserted by the AHB Slave Interface during page register write phase. The following table
gives an overview of minimum idle time for a write operation. The EEPROM controller
programs the data page by page. A page register for write access is used to internally
store the data in a quick way and then a programming cycle can start. The targeted
EEPROM is 16-bit oriented so 32-bit write access need additional processing to combine
two 16-bit access leading to additional wait states.
Table 2.
Wait states for write access on EEPROM
Address
width
Wait states FAST mode
Wait states SLOW mode
AHB
clock cycles
20 MHz Clock
AHB
clock cycles
20 MHz Clock
32-bit
5
250 ns
7
350 ns
8/16-bit
2
100 ns
3
150 ns
The Write operation to the EEPROM has to be done in two steps:
1. Write the 64-Byte short term storage page register.
2. Program the page register in one row of the EEPROM matrix.
