NXP Semiconductors
UM10858
PN7462 family HW user manual
UM10858
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© NXP B.V. 2018. All rights reserved.
User manual
COMPANY PUBLIC
Rev. 1.4 — 14 May 2018
314514
126 of 345
10.3 Register overview and description
10.3.1 Random number generator register overview
Table 145. Random number generator register overview (base address 0x4001 8000)
Name
Address
offset
Width
(bits)
Access
Reset value
Description
RNG_STATUS_REG
00h
16
R
8F00h
random number status register
RNG_CONTROL_REG
04h
16
R/W
2600h
random number control register
RESERVED
08h
4
R/W
0h
Reserved
10.3.2 Register description
Table 146. RNG_STATUS_REG
Bit
Symbol
Access
Value
Description
31:16 RESERVED
-
0x00.
Reserved
15:8
rng
R
Ox8F
RNG number. Updated at each clock cycle but only considered
random if rng_ready is high
7:3
RESERVED
-
0x00.
Reserved
2
rng_ready
R
0.
1: a new RNG value is available.
0: the current value of RNG_STATUS_REG.rng is not random
1
rng_seed_error
R
0
1: TRNG did not provide the random stream in time. Cleared with
rng_enable rising edge.
0: If rng_seed_ready is high, TRNG is providing a random stream. If
rng_seed_ready is low and rng_enable is high, TRNG is starting up.
0
Rng_seed_ready
R
0
1: seeding process is done and PRNG is providing a new RNG value
every cycle.
0: seeding process is ongoing
Table 147. RNG_CONTROL_REG
Bit
Symbol
Access
Value
Description
31:16 RESERVED
-
0x00.
Reserved
15:8
trng_startup_time
R/W
0x26
Programmable wait time to release gated clocks feeding TRNG.An
internal counter is started when RNG_CONTROL_REG.rng_enable
is set, increments at the speed of clkHFO_div8, stops when it
reaches the RNG_CONTROL_REG.trng_startup_time value and
resets when RNG_CONTROL_REG.rng_enable is set low. Default
value is 15.2us.
7:1
RESERVED
-
0x00
reserved
0
rng_enable
R/W
0
1: enable PRNG (clkHFO is released)
0: disable PRNG (clkHFO is gated)
