NXP Semiconductors PCA9665, Product Data Sheet, Page: 77 / 91

PCA9665_2 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 7 December 2006 77 of 91
NXP Semiconductors
PCA9665
Fm+ parallel bus to I
2
C-bus controller
Fig 41. Definition of timing on the I
2
C-bus
SDA
SCL
002aab271
t
f
S
Sr
P S
t
HD;STA
t
LOW
t
r
t
SU;DAT
t
f
t
HD;DAT
t
HIGH
t
SU;STA
t
HD;STA
t
SP
t
SU;STO
t
r
t
BUF
Rise and fall times refer to V
IL
and V
IH
.
Fig 42. I
2
C-bus timing diagram
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
002aac696
protocol
START
condition
(S)
bit 7
MSB
bit 6 bit n bit 0
acknowledge
(A)
1
/f
SCL
t
r
t
VD;DAT
t
SU;STO
STOP
condition
(P)