NXP Semiconductors P4080, User Manual, Page: 56 / 60

P4080 Development System User’s Guide, Rev. 0
56 Freescale Semiconductor
Programming Model
NOTE
The PX_WATCH register represents the 8 most significant bits of an
internal 34-bit watchdog timer. Any new value must be written before the
PX_VCTL[WDEN] bit is set to 1, and must be written after every reset of
this register (that is, it resets just like any other general register).
If the watchdog times out or any other reset/restart condition occurs (except
the PX_VCTL[GO] bit), then repeat the procudure.
Time formulae:
The base of the timer = 26 bits x 30 ns interval = 2.01326592 seconds.
Where the upper 8 bits represent (seconds) [(decimal value of the 8-bit field) x (2.01326592sec)] +
2.01326592sec
Some examples values for PX_WATCH register values are shown in Table 41 .
Offset 0x1F Access: Read/Write
0 7
R
WVAL
W
Reset All ones
Figure 43. Watchdog Register (PX_WATCH)
Table 40. PX_WATCH Field Descriptions
Bits Name Description
0–7 WVAL Read: Returns the current programmed values.
Write: Sets watchdog timer.
Table 41. Watchdog Timer Values
Timeout Value
Timeout
Binary Hex
11111111 0xFF 0.59 min
01111111 0x7F 4.29 min
00111111 0x3F 2.15min
00011111 0x1F 1.07 min
00001111 0x0F 32.1 sec
00000111 0x07 16.1 sec
00000011 0x03 8.05 sec
00000001 0x01 4.027 sec
00000000 0x00 2.013 sec