NXP Semiconductors OM13541 User Manual Download Page 12 | Manualshive

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NXP Semiconductors OM13541 User Manual Download Page 12

NXP Semiconductors

UM11099

PCAL6534 demonstration board OM13541

UM11099

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2019. All rights reserved.

User manual

Rev. 1.0 — 1 August 2019

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6 PCAL6534 evaluation steps with Fm+ development board

The PCAL6534 is controlled by the Fm+ development board GUI in Expert mode as

and

Figure 6. Select the Expert Mode from Fm+ development board GUI (1 of 2)

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Summary of Contents for OM13541

Page 1: ...Manual for the OM13541 34 bit GPIO Daughter Card that connects to OM13260 Fm I2C bus development board This daughter board makes it easy to test and design with the PCAL6534 an ultra low voltage trans...

Page 2: ...tration board OM13541 UM11099 All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 2 29 Revision history Rev Dat...

Page 3: ...and GPIO expansion between 0 8 V to 3 6 V on SCL SDA and 1 8 V 2 5 V 3 3 V 5 5 V on I O ports with active low reset input control and open drain active low interrupt output indicator red LED plus one...

Page 4: ...C bus Development board Easy to use GUI based software demonstrates the capabilities of the PCAL6534 Jumper configuration for most features of PCAL6534 Flexible power supply configuration 3 3 V 5 V o...

Page 5: ...lable 3 2 SCL and SDA jumpers The I 2 C bus signals SDA and SCL supplied to the device under test can be sourced from either the Fm board via J11 or the tester via J1 Jumpers J10 and J9 select the I 2...

Page 6: ...This connector provides power I 2 C signals and other ancillary signals Table 2 J11 18 pin Fm board connector J11 Pin Function Board connection 1 2 9 10 17 18 GND Ground 3 SCL2 SCL Bus 2 to J9 pin 3...

Page 7: ...ed TP4 INT is connected to interrupt output U1 pin B1 for probing use TP1 and TP5 are GND test points for probing use TP6 EXT_OSC is external clock input through J17 1 2 to P2_0 pin E3 for debouncer c...

Page 8: ...ard 2 3 select SCL2 bus 2 from Fm development board J10 3 pin 1 2 SDA SDA1 This jumper is used to select SDA source for U1 device pin A2 1 2 select SDA1 bus 1 from Fm development board 2 3 select SDA2...

Page 9: ...534 demonstration board OM13541 UM11099 All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 9 29 Figure 3 PCAL6...

Page 10: ...N 3V3 5V_PWR VDDI_IN VDDP_IN VDDP_IN VDDP_IN VDDP_IN VDDP_IN VDDP_IN 5V 3V3 3V3 5V VDDI VDDP_IN VDDI_IN Drawing Title Size Document Number Rev Date Sheet of Page Title ICAP Classification CP IUO PUBI...

Page 11: ...mation at the NXP web site https www nxp com products analog interfaces ic bus ic led controllers ic fm plus development board OM13320 5 2 OM13541 connection to Fm I 2 C bus development board The OM13...

Page 12: ...to legal disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 12 29 6 PCAL6534 evaluation steps with Fm development board The PCAL6534 is controlled by the Fm development boa...

Page 13: ...ard hardware is correctly connected to the USB port and the computer recognizes it the message USB I2C Hardware Detected is displayed on the bottom of the window 6 1 PCAL6534 output shifting pattern d...

Page 14: ...Ports 0 to 3 46 Write Yes 200 05 BF BF BF BF Comments set bit6 to 0 in Ports 0 to 3 46 Write Yes 200 05 7F 7F 7F 7F Comments set bit7 to 0 in Ports 0 to 3 Sequence 01 02 03 04 05 06 07 08 09 10 3 Aft...

Page 15: ...is subject to legal disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 15 29 Figure 9 Device selection screen for PCAL6534 2 Input registers read are shown in Figure 10 Fig...

Page 16: ...disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 16 29 Figure 11 Device configuration screen for registers 05 09 hex 4 Polarity registers read or write are shown in Figur...

Page 17: ...disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 17 29 Figure 13 Device configuration screen for registers 0F 13 hex 6 Drive strength registers read or write are shown in...

Page 18: ...disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 18 29 Figure 15 Device configuration screen for registers 3A 3E hex 8 PU PD Enable registers read or write are shown in...

Page 19: ...mers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 19 29 Figure 17 Device configuration screen for registers 44 48 hex 10 Interrupt mask registers read or write are shown in Figur...

Page 20: ...al disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 20 29 Figure 19 Device configuration screen for registers 53 hex 12 Interrupt edge registers read or write are shown i...

Page 21: ...l disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 21 29 Figure 21 Device configuration screen for registers 5E 62 hex 14 Input status registers read are shown in Figure...

Page 22: ...his document is subject to legal disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 22 29 Figure 23 Device configuration screen for registers 68 6C hex 16 Debounce register...

Page 23: ...ration board OM13541 UM11099 All information provided in this document is subject to legal disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 23 29 7 Support For support pl...

Page 24: ...hts reserved User manual Rev 1 0 1 August 2019 24 29 8 Abbreviations Table 5 Abbreviations Acronym Description ESD Electro Static Discharge GPIO General Purpose Input Output GUI Graphical User Interfa...

Page 25: ...ment is subject to legal disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 25 29 9 References 1 PCAL6534 Ultra low voltage translating 34 bit Fm I 2 C bus SMBus I O expand...

Page 26: ...ucts using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whe...

Page 27: ...ubject to legal disclaimers NXP B V 2019 All rights reserved User manual Rev 1 0 1 August 2019 27 29 Tables Tab 1 J1 10 pin tester connector 6 Tab 2 J11 18 pin Fm board connector 6 Tab 3 J12 J13 J14 J...

Page 28: ...e selection screen for PCAL6534 15 Fig 10 Device configuration screen for registers 00 04 hex 15 Fig 11 Device configuration screen for registers 05 09 hex 16 Fig 12 Device configuration screen for re...

Page 29: ...3541 34 bit GPIO daughter board 4 3 Hardware description 5 3 1 Power supply jumpers 5 3 2 SCL and SDA jumpers 5 3 3 Device reset interrupt and address pin selection 5 3 4 Board layout viewer 5 3 5 Con...

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