NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 875 / 1761

Address: 4007_6000h base + 18Ch offset = 4007_618Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TPADB2 Reserved
W
Reset
* * * * * * * * * * * * * * * * * * * * * * 0 0 0 0 0 0 0 0 0 0
* Notes:
TPADB2 field: See the module configuration for the device specific reset values. •
QuadSPI_SFB2AD field descriptions
Field Description
31–10
TPADB2
Top address for Serial Flash B2. In effect, TPxxAD is the first location of the next memory.
Reserved This field is reserved.
33.4.2.30 RX Buffer Data Register (QuadSPI_RBDRn)
The QuadSPI_RBDR registers provide access to the individual entries in the RX Buffer.
Refer to
Table 33-16 for the byte ordering scheme.
QuadSPI_RBDR0 corresponds to the actual position of the read pointer within the RX
Buffer. The number of valid entries available depends from the number of RX Buffer
entries implemented and from the number of valid buffer entries available in the RX
Buffer.
Example 1, RX Buffer filled completely with 32 words: In this case the address range for
valid read access extends from QuadSPI_RBDR0 to QuadSPI_RBDR31.
Example 2, RX Buffer filled with 5 valid words: RX Buffer fill level
QuadSPI_RBSR[RDBFL] is 5. In this case an access to QuadSPI_RBDR4 provides the
last valid entry.
Any access beyond the range of valid RX Buffer entries provides undefined results.
Address: 4007_6000h base + 200h (4d × i), where i=0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RXDATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QuadSPI_RBDRn field descriptions
Field Description
RXDATA RX Data. The RXDATA field contains the data associated with the related RX Buffer entry. Data format
and byte ordering is given in
Byte Ordering of Serial Flash Read Data .
Chapter 33 Quad Serial Peripheral Interface (QuadSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 875