NXP Semiconductors MWCT101 S Series, Reference Manual

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33.4.2.10 Buffer0 Top Index Register (QuadSPI_BUF0IND)
This register specifies the top index of buffer0, which defines its size. Note that that the 3
LSBs of this register are set to zero. This ensures that the buffer is 64-bit aligned, as each
buffer entry is 64 bits long.
The register value should be set to the desired number of bytes. For example, setting
BUF0IND[31:3] to 0 gives 0 bytes, 1 gives 8 bytes etc.
The size of buffer0 is the difference between BUF0IND and 0.
Software should ensure that BUF0IND value is not greater than the overall size of the
buffer. The hardware does not provide any protection against illegal programming.
Write:
• QSPI_SR[AHB_ACC] = 0
Address: 4007_6000h base + 30h offset = 4007_6030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
TPINDX0 Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
QuadSPI_BUF0IND field descriptions
Field Description
31–3
TPINDX0
Top index of buffer 0.
Reserved This field is reserved.
Reserved.
33.4.2.11 Buffer1 Top Index Register (QuadSPI_BUF1IND)
This register specifies the top index of buffer1, which defines its size. Note that the 3
LSBs of this register are set to zero. This ensures that the buffer is 64-bit aligned as each
buffer entry is 64 bits long.
The size of buffer1 is the difference between BUF1IND and BUF0IND. The register
value should be entered in bytes. For example, If BUF0IND = 0x100 then setting
BUF1IND = 0x130 will set buffer1 size to 0x30 bytes.
It is the responsibility of the software to ensure that BUF1IND value is not greater than
the overall size of the buffer. The hardware does not provide any protection against
illegal programming.
Chapter 33 Quad Serial Peripheral Interface (QuadSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 851