NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 493 / 1761

Chapter 24
Reset Control Module (RCM)
24.1 Chip-specific RCM information
High voltage detect reset is not supported on this device. The SACKERR timing is 0.5 s.
On this device, LVD (Low voltage detect) and LVR (Low voltage reset) events trigger
LVD reset and hence Chip POR. Chip POR is triggered by POR, LVR or LVD events.
The PMC_LVDSC1[LVDRE] is used to gate LVD only, and has no effect on LVR
generation. With PMC_SC1[LVDRE] disabled, LVRs can still generate reset to system.
See
Low Voltage Detect (LVD) System .
Wait mode is not supported on this device. See Module operation in available power
modes for details on available power modes.
LPO128K_CLK is used as low power clock for reset pin filter.
See Arm Cortex-M4 Devices Generic User Guide for details on 'lockup' event.
24.2 Reset pin filter operation in STOP1/2 modes
The reset pins filtering in STOP1/2 mode is as follows:
• STOP1: Both RUN mode and STOP mode filters can operate. The filter with lower
pulse duration dominates.
• STOP2: RUN mode filter operates.
24.3 Introduction
Information found here describes the registers of the Reset Control Module (RCM). The
RCM implements many of the reset functions for the chip. See the chip's reset chapter for
more information.
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 493