NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 340 / 1761

16.4.5.24.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SMLOE
DMLOE
MLOFF
W
Reset
u u u u u u u u u u u u u u u u
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MLOFF NBYTES
W
Reset u u u u u u u u u u u u u u u u
16.4.5.24.4 Fields
Field Function
31
SMLOE
Source Minor Loop Offset Enable
Selects whether the minor loop offset is applied to the source address upon minor loop completion.
0b - The minor loop offset is not applied to the SADDR
1b - The minor loop offset is applied to the SADDR
30
DMLOE
Destination Minor Loop Offset enable
Selects whether the minor loop offset is applied to the destination address upon minor loop completion.
0b - The minor loop offset is not applied to the DADDR
1b - The minor loop offset is applied to the DADDR
29-10
MLOFF
If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or
destination address to form the next-state value after the minor loop completes.
9-0
NBYTES
Minor Byte Transfer Count
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible
operation and cannot be halted. It can, however, be stalled by using the bandwidth control field, or via
preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the
TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major
iteration count is completed, additional processing is performed.
16.4.5.25 TCD Last Source Address Adjustment (TCD0_SLAST -
TCD15_SLAST)
16.4.5.25.1 Offset
For n = 0 to 15:
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
340 NXP Semiconductors